Publications

Technical Reports

Edward J. McCluskey

Technical Reports

  1. Huang, W.-J., S. Mitra, and E.J. McCluskey, "Fast Run-Time Fault Location in Dependable FPGAs," CRC TR 01-5, May 2001.
  2. Shirvani, P.P., and E.J. McCluskey, "SEU Characterization of Digital Circuits Using Wighted Test Programs," CRC TR 01-4, May 2001.
  3. Shirvani, P.P., N.R. Saxena, and E.J. McCluskey, "Software-Implemented EDAC Protection Against SEUs," CRC TR 01-3, May 2001.
  4. Yu, S.-Y., and E.J. McCluskey, "Permanent Fault Repair for FPGAs with Limited Redundant Area," CRC TR 01-2, May 2001.
  5. Mitra S., N.R. Saxena, and E.J. McCluskey, "Techniques for Calculation of Design Diversity for Combinational Logic Circuits," CRC TR 01-1, March 2001.
  6. Oh, N., S. Mitra, and E.J. McCluskey, "ED4I: Error Detection by Diverse Data and Duplicated Instructions," CRC TR 00-8, Nov. 2000.
  7. Shirvani, P.P., and E.J. McCluskey, "PADded Cache: A New Fault Tolerance Technique for Cache Memories," CRC TR 00-6, Apr. 2000.
  8. Mitra, S., L.J. Avra, and E.J. McCluskey, "Efficient Multiplexer Synthesis," CRC TR 00-3, Mar. 2000.
  9. Mitra, S., and E.J. McCluskey, "Design of Redundant Systems Protected Against Common-Mode Failures," CRC TR 00-2, Feb. 2000.
  10. Li, J.C.M., J.T.-Y. Chang, C.W. Tseng, and E.J. McCluskey, "ELF1 Experiment - Chip and Experiment Design,"CRC TR 99-3, Oct. 1999.
  11. Shirvani, P.P., and E.J. McCluskey, " Fault-Tolerant Systems in a Space Environment: The CRC ARGOS Project," CRC TR 98-2, December 1998.
  12. Norwood, R.B., and E.J. McCluskey, "Delay Testing for Sequential Circuits with Scan," CRC TR 97-5, Nov. 1997.
  13. Norwood, R.B., and E.J. McCluskey, "Merged Orthogonal Scan," CRC TR 97-4, Nov. 1997.
  14. Norwood, R.B., and E.J. McCluskey, " Synthesis-for-Scan and Scan Path Ordering," CRC TR 97-3, Nov. 1997.
  15. Touba, N.A., and E.J. McCluskey, " Test Point Insertion for Non-Feedback Briding Faults," CRC TR 96-3.
  16. Makar, S.R., and E.J. McCluskey, "Some Faults Need an IDDQ Test," CRC TN 96-1, Aug. 1996.
  17. Ma, S.C., and E.J. McCluskey, "Design-for-Current-Testability (DFCT) for Dynamic CMOS Logic," CRC TR 94-13.
  18. Mukund, S.K., E.J. McCluskey, and T.R.N. Rao, "An Apparatus for Pseudo-Deterministic Testing," CRC TR 94-12.
  19. Makar, S., and E.J. McCluskey, "Using Checking Experiments To Test D-Latches," CRC TR 94-11.
  20. Touba, N.A., and E.J. McCluskey, "Transformed Pseudo-Random Patterns for BIST," CRC TR 94-10.
  21. Franco, P., "Testing Digital Circuits for Timing Failures by Output Waveform Analysis," CRC TR 94-9.
  22. Avra, L.J., "Synthesis Techniques for Built-In Self-Testable Designs," CRC TR 94-7.
  23. Franco, P., R.L. Stokes, W.D. Farwell, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Part 1: Description of Experiment," CRC TR 94-5, June 1994.
  24. Franco, P., and E.J. McCluskey, "WSIM: A Symbolic Waveform Simulator," CRC TR 94-4, June 1994.
  25. Avra, L.J., L. Gerbaux, J.-C. Giomi, F. Martinolle, and E.J. McCluskey, "A Synthesis-for-Test Design System," CRC TR 94-3, Stanford University, Stanford, CA, May 1994. (Link to Stanford CSD Electronic Library)
  26. Avra, L.J., and E.J. McCluskey, "Synthesis for Scan Dependence in Built-In Self-Testable Designs," CRC TR 94-2, Stanford University, Stanford, CA, May 1994. (Link to Stanford CSD Electronic Library)
  27. Franco, P., and E.J. McCluskey, "On-Line Delay Testing of Digital Circuits," CRC TR 93-7, Nov. 1993.
  28. Touba, N.A., and E.J. McCluskey, " Logic Synthesis for Concurrent Error Detection," CRC TR 93-6, Nov. 1993.
  29. Pan, R., N.A. Touba, and E.J. McCluskey, "The Effect of Fault Dropping on Fault Simulation Time," CRC TR 93-5.
  30. Ma, S., and E.J. McCluskey, "Open Faults in BiCMOS Gates," CRC TR 93-4, Nov. 1993.
  31. Hao, H., and E.J. McCluskey, "Very-Low-Voltage Testing for Weak CMOS Logic IC's," CRC TR 93-1, Apr. 1993.
  32. Ma, S., and E.J. McCluskey, "Non-Conventional Faults in BiCMOS Digital Circuits," CRC 92-2, Aug. 1992.
  33. Hao, H., and E.J. McCluskey, "Analysis of Gate Oxide Shorts in CMOS Circuits," CRC TR 92-1, Jan. 1992.
  34. Saxena, N.R., E.J. McCluskey, and S. Makar, "Linear Complexity Assertions for Sorting Algorithms," CRC TR 91-3, Feb. 1991.
  35. Saxena, N.R., E.J. McCluskey, and P. Franco, "Refined Bounds on Signature Analysis Aliasing for Random Testing," CRC TR 91-2, Feb. 1991.
  36. Hao, H., and E.J. McCluskey, "Resistive Shorts Within CMOS Gates," CRC TR 91-1, Feb. 1991.
  37. Saxena, N.R., E.J. McCluskey, and P. Franco, "Bounds on Signature Analysis Aliasing for Random Testing," CRC TR 90-11, Dec. 1990.
  38. Makar, S.R., and E.J. McCluskey, "Implementing Fault Models in Verilog," CRC TR 90-7, Nov. 1990.
  39. Fukazawa, T., and E.J. McCluskey, "Assertions for Dynamic Error Detection on a Parallel Processor," CRC TR 90-5, Nov. 1990.
  40. Makar, S.R., and E.J. McCluskey, "Minimal Single Stuck-at Tests For Multiplexers," CRC TR 90-3, June 1990.
  41. Avra, L., and E.J. McCluskey, "On the Behavioral Synthesis of Testable Systems with VHDL," CRC TR 90-2, May 1990.
  42. Yamamura, H., and E.J. McCluskey, "Fault Analysis of ECL Gates with Device Defects using SPICE," CRC TR 90-1, Mar. 1990.
  43. Millman, S.D., J.M. Acken, and E.J. McCluskey, "Diagnosing CMOS Bridging Faults with Stuck-At Fault Dictionaries," CRC TR 89-8, Dec. 1989.
  44. Millman, S.D., and E.J. McCluskey, "Pseudorandom Test for Bridging Faults," CRC TR 89-7, Dec. 1989.
  45. Millman, S.D., and E.J. McCluskey, "Bridging, Transition, and Stuck-Open Faults in Self-Testing CMOS Checkers," CRC TR 89-6, Dec. 1989.
  46. Millman, S.D., and E.J. McCluskey, "Detecting Stuck-Open Faults with Stuck-At Test Sets," CRC TR 89-5, Dec. 1989.
  47. Hao, H., and E.J. McCluskey, "Survey of Combinational Shifter Implementations," CRC TR 89-4, Oct. 1989.
  48. Udell, J.G. Jr., and E.J. McCluskey, "Pseudo-Exhaustive Test and Segmentation: Formal Definitions and Extended Fault Coverage Results," CRC TR 88-12, Dec. 1988.
  49. Udell, J.G. Jr., and E.J. McCluskey, "An Efficient Segmentation Program for Pseudo-Exhaustive Test," CRC TR 88-11, Dec. 1988.
  50. Udell, J.G. Jr., and E.J. McCluskey, "Circuit Reduction for Efficient Segmentation," CRC TR 88-10, Dec. 1988.
  51. Saxena, N., and E.J. McCluskey, "Analysis of Checksums, Extended-Precision Checksums and Cyclic Redundancy Checks," CRC TR 88-9, Sep. 1988.
  52. Amer, H.A., and E.J. McCluskey, "Safe and Unsafe faults in CMOS Exclusive-Or Gates with Gate Oxide Shorts," CRC TR 88-8, Sep. 1988.
  53. Udell, J.G., and E.J. McCluskey, "Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation," CRC TR 88-7, Sep. 1988.
  54. Marhoefer, M., and E.J. McCluskey, "An Experimental Study of Supergates," CRC TR 88-6.
  55. McCluskey, E.J., "Design Techniques for Testable Embedded Error Checkers," CRC TR 88-4.
  56. Côrtes, M.L., S.D. Millman, H.A. Goosen, and E.J. McCluskey, "Techniques for Injecting Non Stuck-At Faults," CRC TR 87-21, Mar. 1987.
  57. Millman, S.D., and E.J. McCluskey, "Detecting Bridging Faults with Stuck-at Test Sets," CRC TR 87-20, Dec. 1987.
  58. Wakerly, J.F., and E.J. McCluskey, "Logic Design Education at Stanford University," CRC TR 87-19, Oct. 1987.
  59. Goosen, H.A., M.L. Côrtes, and E.J. McCluskey, "Design of the Detector II: A CMOS Gate Array for the Study of Concurrent Error Detection Techniques," CRC TR 87-17, July 1987.
  60. McCluskey, E.J., "Exhaustive and Pseudo-Exhaustive Testing," CRC TR 87-13, July 1987.
  61. Amer, H.H., M.L. Cortes, and E.J. McCluskey, "Inadequacy of Conventional Dynamic recovery Machanisms in the Presence of Temporary Failures," CRC TR 87-11, June 1987.
  62. Liu, D.L., and E.J. McCluskey, "CMOS Scan-Path IC Design for Stuck-Open Fault Testability," CRC TR 87-10, June 1987.
  63. Liu, D.L., and E.J. McCluskey, "Designing CMOS Combinational Circuits for Switch-Level Testability," CRC TR 87-9, June 1987.
  64. Amer, H.H., and E.J. McCluskey, "Weighted Coverage in Fault-Tolerant Systems," CRC TR 87-8, May 1987.
  65. Côrtes, M.L., and E.J. McCluskey, "An Experiment on Intermittent-Failure Mechanisms," CRC TR 87-7, Mar. 1987.
  66. McCluskey, E.J., "Short Pseudorandom Test Sequences," CRC TR 87-6, Feb. 1987.
  67. Shperling, I., and E.J. McCluskey, "Circuit Segmentation for Pseudo-Exhaustive Testing Via Simulated Annealing," CRC TR 87-2, Feb. 1987.
  68. Sakov, J., and E.J. McCluskey, "Functional Test Pattern Generation for Random Logic," CRC TR 87-1, Feb. 1987.
  69. Wagner, K., and E.J. McCluskey, "Effect of Supply Voltage on Circuit Propagation Delay and Test Applications," CRC TR 86-21, Dec. 1986.
  70. McCluskey, E.J., "Complete Feedback Shift Register Design for Built-In Self-Test," CRC TR 86-17, Nov. 1986.
  71. McCluskey, E.J., "VLSI Technology Research at Stanford," CRC TR 86-13, June 1986.
  72. McCluskey, E.J., "Hardware Fault Tolerance," CRC TR 86-11, July 1986.
  73. Wang, L.-T., and E.J. McCluskey, "Circuits for Pseudo-Exhaustive Test Pattern Generation Using Cyclic Codes," CRC TR 86-8, July 1986.
  74. Mourad, S., J.L.A. Hughes, and E.J. McCluskey, "Stuck-At Fault Detection in Parity Trees," CRC TR 86-7, June 1986.
  75. Wagner, K., C. Chin, and E.J. McCluskey, "Pseudorandom Testing," CRC TR 86-6, June 1986.
  76. Freeman, G.G., D.L. Liu, B. Wooley, and E.J. McCluskey, "Two CMOS Metastability Sensors," CRC TR 86-4, May 1986.
  77. McCluskey, E.J., "Reliable Digital Systems," CRC TR 86-3, May 1986.
  78. McCluskey, E.J., "Comparing Causes of IC Failures," CRC TR 86-2, May 1986.
  79. Wang, L.-T., and E.J. McCluskey, "Condensed Linear Feedback Shift Register (LFSR) Testing -- A Pseudo-Exhaustive Test Technique," CRC TR 85-24, Dec. 1985.
  80. Mourad, S., J.L.A. Hughes, and E.J. McCluskey, "Stuck-At Fault Detection in Parity Trees," CRC TR 85-23, Dec. 1985.
  81. Andrews, D.M., A. Mahmood, and E.J. McCluskey, "A Methodology for Testing Fault-Tolerant Software," CRC TR 85-22, Nov. 1985.
  82. Bozorgui-Nesbat, S., and E.J. McCluskey, "Verification Testing of Programmable Logic Arrays," CRC TR 85-19, Nov. 1985.
  83. Andrews, D.M., and E.J. McCluskey, "The Measurement and Modeling of Computer Reliability as Affected by System Activity," CRC TR 85-18, Nov. 1985.
  84. McCluskey, E.J., "A Comparison of Test Pattern Generation Techniques," CRC TR 85-16, Dec. 1985.
  85. Andrews, D.M., A. Mahmood, and E.J. McCluskey, "Dynamic Assertion Testing of Flight Control Software," CRC TR 85-15.
  86. McCluskey, E.J., "Delay Testing of Digital Circuits Using Pseudorandom Input Sequences," CRC TR 85-12, Sep. 1985.
  87. Ersoz, A., D.M. Andrews, and E.J. McCluskey, "The Watchdog Task: Concurrent Error Detection Using Assertions," CRC TR 85-8.
  88. McCluskey, E.J., "Design for Testability Reprints," CRC TR 85-6, June 1985.
  89. Chin, C.K., and E.J. McCluskey, "Weighted Pattern Generation for Built-in Self-Test," CRC TR 84-7.
  90. Wagner, K.D., and E.J. McCluskey, "Tuning, Clock Distribution and Communication in VLSI High-Speed Chips," CRC TR 84-5.
  91. Hassan, S.Z., and E.J. McCluskey, "Increasing Effective Fault Coverage of Parallel Signature Analyzers," CRC TR 84-3.
  92. McCluskey, E.J., D.J. Lu, S. Bozorgui-Nesbat, and A. Mahmood, "Testing VHSIC Devices," CRC TR 84-1, Jan. 1984.
  93. Dong, H., and E.J. McCluskey, "Concurrent Testing of Programmable Logic Arrays," CRC TR 82-11, June 1982.
  94. Khakbaz, J., and E.J. McCluskey, "Self-testing Embedded Parity Checkers -- Exhaustive XOR Gate Testing," CRC TR 82-10, June 1982.
  95. Namjoo, M., and E.J. McCluskey, "Watchdog Processors and Capability Checking," CRC TR 82-3.
  96. McCluskey, E.J., "A Discussion of Multiple-valued Logic Circuits," CRC TR 82-2, Mar. 1982.
  97. Dong, H., and E.J. McCluskey, "Design of Fully Testable Programmable Logic Arrays," CRC TR 81-20, Dec. 1981.
  98. Namjoo, M., and E.J. McCluskey, "Watchdog Processors and Detection of Malfunctions at the System Level," CRC TR 81-17, Dec. 1981.
  99. Dong, H., and E.J. McCluskey, "Matrix Representation of PLA's and an Application to Characterizing Errors," CRC TR 81-11, Sep. 1981.
  100. Iyer, R.K., S.E. Butner, and E.J. McCluskey, "An Exponential Failure/Load Relationship: Results of a Multi-computer Statistical Study," CRC TR 81-6, July 1981.
  101. McCluskey, E.J., "Testing VHSIC Devices," CRC TR 81-3, July 1981.
  102. McCluskey, E.J., "Reliable Computing Systems," CRC TN 182, Oct. 1980.
  103. Lu, D.J., E.J. McCluskey, and M. Namjoo, "Summary of Structural Integrity Checking," CRC TN 181, Sep. 1980.
  104. McCluskey, E.J., and S. Bozorgui-Nesbat, "Design for Autonomous Test," CRC TN 180, Aug. 1980.
  105. McCluskey, E.J., and J.F. Wakerly, "A Circuit for Detecting and Analyzing Temporary Failures," CRC TN 178, Aug. 1980.
  106. Hayes, J.P., and E.J. McCluskey, "Testability Considerations in Microprocessor-Based Design," CSL TN 179, Nov. 1979.
  107. McCluskey, E.J., "Fault-tolerant Computing Systems," CSL TN 170, Nov. 1979.
  108. McCluskey, E.J., "Designing with PLA's," CSL TN 168, Nov. 1979.
  109. McCluskey, E.J., "Testing Digital Circuits and Systems," CSL TN 166, Sep. 1979.
  110. McCluskey, E.J., "Research in Digital Systems Laboratory," CSL TN 150, Jul. 1977.
  111. McCluskey, E.J., "Design for Maintainability and Testability," CSL TN 145, Sep. 1978.
  112. McCluskey, E.J., "Reliability and Computer Architecture," CSL TN 122, Dec. 1977.
  113. McCluskey, E.J., J.F. Wakerly, and R.C. Ogus, "Center for Reliable Computing: Current Research," CSL TR 100, Oct. 1975.
  114. McCluskey, E.J., "A Survey of Research at the Center for Reliable Computing, Stanford University, CSL TN 96, Oct. 1976.
  115. McCluskey, E.J., "A Survey of Research at the Center for Reliable Computing, Stanford University, CSL TN 95, Aug. 1976.
  116. Shedletsky, J.J., and E.J. McCluskey, "The Error Latency of a Fault in a Combinational Digital Circuit," CSL TN 55.
  117. Matarai, H., and E.J. McCluskey, "Design of a Parallel Encoder/Decoder for the Hamming Code Using ROM," CSL TR 36, June 1972.
  118. Siewiorek, D.P., and E.J. McCluskey, "A Measure of Switch Complexity in Systems with Standby Spares," CSL TR 21, Dec. 1971.
  119. Siewiorek, D.P., and E.J. McCluskey, "An Iterative Cell Switch Design for Hybrid Redundancy," CSL TR 20, Dec. 1971.
  120. Siewiorek, D.P., and E.J. McCluskey, "Switch Designs for Hybrid Redundancy," CSL TN 13.
  121. McCluskey, E.J., and F.W. Clegg, "Fault Equivalence in Combinational Logic Networks," CSL TN 10, Mar. 1971.
  122. Bredt, T.H., and E.J. McCluskey, "On the Necessity of Mutual Exclusion for Mutual Exclusion," CSL TN 6, Nov. 1970.
  123. Bredt, T.H., and E.J. McCluskey, "A Model for Parallel Computer Systems," CSL TR 5, Apr. 1970.
  124. Clegg, F.W., and E.J. McCluskey, "Algebraic Properties of Faults in Logic Networks," CSL TR 4, Mar. 1970.
  125. Belden, T.G, R. Bozak, W.L. Chadwell, L.S. Christie, J.P. Haverty, E.J. McCluskey, R.H. Scherer, and W.S. Torgerson, "Computers in Command and Control," Tech. Rpt. No. 61-62, Institute for Defense Analyses, Arlington, Virginia, Nov. 1961.
  126. Bryan, G.E., E.J. McCluskey, and I.D. Nehama, "A System Plan for a 50,000 Line Electronic Switching System - P - Case 36279-1," Bell Telephone Laboratories Technical Memorandum, Jan. 1, 1958.
  127. McCluskey, E.J., "Limitations on the Use of Negative Resistance to Improve Transmission Through the ESS Switching Network - Case 36279-4," Bell Telephone Laboratories Technical Memorandum, June 26, 1956.

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Last modified: Mon Jul 9 14:05:32 PDT 2001