Publications

Edward J. McCluskey

Books

  1. Logic Design Principles, Prentice-Hall Inc., Englewood Cliffs, N.J., 1986.
  2. "Reliable Digital Systems and Related Stanford University Research," The Evolution of Fault-Tolerant Computing, Springer-Verlag Wien, Austria.
  3. Design of Digital Computers, Springer-Verlag, New York, New York, 1975. (with H.W. Gschwind)
  4. Introduction to the Theory of Switching Circuits, McGraw-Hill Book Co., New York, New York, 1965.
  5. A Survey of Switching Circuit Theory, McGraw-Hill Book Co., New York, New York, 1962. (with T.C. Bartee)

Book Contributions

  1. "Logic Design," in Encyclopedia of Computer Science and Engineering, 4th Ed. Anthony Ralston, Edwin D. Reilly, and David Hemmendinger, Eds, pp. 1014-1016, Grove's Dictionary, Inc., New York, 2000
  2. "Switching Theory," in Encyclopedia of Computer Science and Engineering, 4th Ed. Anthony Ralston, Edwin D. Reilly, and David Hemmendinger, Eds, pp. 1727-1731, Grove's Dictionary, Inc., New York, 2000
  3. "Logic Design," in Reference Data for Engineers: Radio, Electronics,Computer, and Communications, 8th Ed., Chapter 43, Van Valkenburg, Ed., Howard W. Sams & Co., Inc., Indianapolis, 1993.
  4. "Logic Design," in Encyclopedia of Computer Science and Engineering, 3rd Ed. Anthony Ralston and Edwin D. Reilly, Eds, pp. 775-778, Van Nostrand Reinhold, New York, 1993.
  5. "Switching Theory," in Encyclopedia of Computer Science and Engineering,3rd Ed., Anthony Ralston and Edwin D. Reilly, Eds., pp. 1332-1336, Van Nostrand Reinhold, New York, 1993.
  6. "Half a Century of Logic Synthesis," in Logic and Architecture Synthesis, pp. 3-8, P. Michel and G. Saucier, Ed., North-Holland, 1991.
  7. "Foreword" in Structured Logic Testing, Prentice Hall Inc., Englewood Cliffs, NJ, 1990.
  8. "Fault Models," in Testing and Diagnosis of VLSI and ULSI, pp. 49-68, Kluwer Academic Publishers, 1988.(with S. Mourad )
  9. "Comparing Causes of IC Failure," in Development in Integrated Circuit Testing, M. Miller, ed., Academic Press, pp. 13-46, 1987. (with S. Mourad)
  10. "Design for Testability," in Fault-Tolerant Computing, Vol. 1, Chap. 2, D.K. Pradhan ed., Prentice-Hall Inc., Englewood Cliffs, N.J., 1986.
  11. "Logic Design," in Encyclopedia of Computer Science and Engineering, 3rd Ed. Anthony Ralston and Edwin D. Reilly, Eds, pp. 775-778, Van Nostrand Reinhold, New York, 1980.
  12. "Logic Design," in Encyclopedia of Computer Science, pp. 809-813, A. Ralston and C. Meek, Ed., Petrocelli/Charter, New York, NY, 1976.
  13. "Minimization Theory," in A Survey of Switching Circuit Theory, McGraw-Hill Book Co., New York, New York, pp. 67-88, 1962. (with T.C. Bartee)
  14. "Introduction to State Tables," in A Survey of Switching Circuit Theory, McGraw-Hill Book Co., New York, New York, pp. 109-119, 1962. (with T.C. Bartee)
  15. "Transients in Combinational Logic Circuits," in Redundancy Techniques for Computing Systems, Spartan Books, Washington, D.C., pp. 9-46, 1962. (with R.H. Wilcox and W.C. Mann)
  16. "Fault Tolerance," in Computer Science Handbook, 2nd Ed. Allen B. Tucker, Ed.-in-Chief, pp.25-1-25-20, Chapman & Hall/CRC, (published in Cooperation with ACM, The Association for Computing Machinery,) Florida, 2004 (co-authored with Subhasish Mitra)
  17. "Logic Design," in Concise Encyclopedia of COMPUTER SCIENCE, Edwin D. Reilly, ed., pp.455-458, John Wiley & Sons,Ltd.,West Sussex, England, 2004

Refereed Journals and Conferences

  1. "Techniques for Estimation of Design Diversity for Combinational Logic Circuits," Int. Conf. on Dependable Systems and Networks (DSN'01), pp. 25-34, Goteborg, Sweden, Jul. 1-4, 2001. (with S. Mitra and N.R. Saxena)
  2. "Diagnosis of Tunneling Opens," 19th IEEE VLSI Test Symposium (VTS'01), pp. 22-27, Los Angeles, CA, Apr. 30-May 3, 2001. (with C.M.J. Li)
  3. "Design Diversity for Concurrent Error Detection in Sequential Logic Circuits," 19th IEEE VLSI Test Symposium (VTS'01), pp. 178-183, Los Angeles, CA, Apr. 30-May 3, 2001. (with S. Mitra)
  4. "Design of Redundant Systems Protected Against Common-Mode Failures," 19th IEEE VLSI Test Symposium (VTS'01), pp. 190-195, Los Angeles, CA, Apr. 30-May 3, 2001. (with S. Mitra)
  5. "MINVDD Testing for Weak CMOS ICs," 19th IEEE VLSI Test Symposium (VTS'01), pp. 339-344, Los Angeles, CA, Apr. 30-May 3, 2001. (with C.-W. Tseng, R. Chen, and P. Nigh)
  6. "An Evaluation of Pseudo Random Testing for Detecting Real Defects," 19th IEEE VLSI Test Symposium (VTS'01), pp. 404-409, Los Angeles, CA, Apr. 30-May 3, 2001. (with C.-W. Tseng, S. Mitra, and S. Davidson)
  7. "Bit-Fixing in Pseudorandom Sequences for Scan BIST," IEEE Trans. CAD, Vol. 20, No. 4, pp. 545-555, Apr. 2001. (with N.A. Touba)
  8. "A Memory Coherence Technique for Online Transient Error Recovery of FPGA Configurations," 9th ACM Int. Symposium on Field-Programmable Gate Arrays (FPGA'01), pp. 183-192, Monterey, CA, Feb. 11-13, 2001. (with W.-J. Huang)
  9. "Transient Errors and Rollback Recovery in LZ Compression," 2000 Pacific Rim International Symposium on Dependable Computing (PRDC 2000), pp. 128-135, Los Angeles, CA, Dec. 18-20, 2000. (with W.-J. Huang)
  10. "Dependable Adaptive Computing Systems, The Stanford CRC ROAR Project," 2000 Pacific Rim International Symposium on Dependable Computing Fast Abstracts (PRDC 2000), pp. 15-16, Los Angeles, CA, Dec. 18-20, 2000.(with S. Mitra, W.-J. Huang, N.R. Saxena, and S.-Y. Yu)
  11. "Testing for Tunneling Opens," Proc. 2000 Int. Test Conf., pp. 85-94, Atlantic City, NJ, Oct. 3-5, 2000. (with J.C.M. Li)
  12. "Stuck-Fault Tests vs. Actual Defects," Proc. 2000 Int. Test Conf., pp. 336-343, Atlantic City, NJ, Oct. 3-5, 2000. (with C.-W. Tseng)
  13. "Why Defects Escape some of our Tests," Proc. 2000 Int. Test Conf., p. 1125, Atlantic City, NJ, Oct. 3-5, 2000.
  14. "Combinational Logic Synthesis for Diversity in Duplex Systems," Proc. 2000 Int. Test Conf., pp. 179-188, Atlantic City, NJ, Oct. 3-5, 2000. (with S. Mitra)
  15. "Which Concurrent Error Detection Scheme to Choose?" Proc. 2000 Int. Test Conf., pp. 985-994, Atlantic City, NJ, Oct. 3-5, 2000. (with S. Mitra)
  16. "Efficient Multiplexer Synthesis Techniques," IEEE Design and Test of Computers," Vol. 17, No. 4, pp. 90-97, Oct.-Dec. 2000. (with S. Mitra and L.J. Avra)
  17. "Software-Implemented EDAC Protection Against SEUs," IEEE Trans. on Reliability, Vol. 49, No. 3, pp. 273-284, Sep. 2000. (with P.P. Shirvani and N.R. Saxena)
  18. "Common-Mode Failures in Redundant VLSI Systems: A Survey," IEEE Trans. on Reliability, Vol. 49, No. 3, pp. 285-295, Sep. 2000. (with S. Mitra and N.R. Saxena)
  19. "Fault Escapes in Duplex Systems," 18th IEEE VLSI Test Symposium, pp. 453-458, Montreal, Canada, Apr. 30-May 4, 2000.(with S. Mitra and N.R. Saxena)
  20. "Word-Voter: A New Voter Design for Triple Modular Redundant Systems," 18th IEEE VLSI Test Symposium, pp. 465-470, Montreal, Canada, Apr. 30-May 4, 2000. (with S. Mitra)
  21. "Cold Delay Defect Screening," 18th IEEE VLSI Test Symposium, pp. 183-188, Montreal, Canada, Apr. 30-May4, 2000. (with C.-W. Tseng, X. Shao, J. Wu and D.M. Wu)
  22. "A Reliable LZ Data Compressor on Reconfigurable Coprocessors," FCCM'00 Symposium on Field-Programmable Custom Computing Machines, pp. 249-258, Napa Valley, CA, April 16-19, 2000. (with W.J. Huang and N.R. Saxena)
  23. "ACS Implementation of a Robotic Control Algorithm with Fault Tolerant Capabilities," FCCM'00 Symposium on Field-Programmable Custom Computing Machines, pp. 175-184, Napa Valley, CA, April 16-19, 2000. (with S.-Y. Yu and N.R. Saxena)
  24. "Dependable Computing and Online Testing in Adaptive and Configurable Systems," IEEE Design and Test of Computers, Vol. 17, No. 1, pp. 29-41, Jan.-Mar. 2000. (with N.R. Saxena, S. Fernandez-Gomez, W.J. Huang, S. Mitra, and S.-Y. Yu)
  25. "Non-Self-Testable Faults in Duplex Systems," IEEE High Level Design and Validation Test Workshop (HLDVT'99), pp. 102-109, San Diego, CA, Nov. 4-6, 1999.(with S. Mitra and N.R. Saxena)
  26. "A Design Diversity Metric and Reliability Analysis for Redundant Systems," Proc. 1999 Int. Test Conf., pp. 662-671, Atlantic City, NJ, Sep. 28-30, 1999.(with S. Mitra and N.R. Saxena)
  27. "Finite State Machine Synthesis with Concurrent Error Detection," Proc. 1999 Int. Test Conf., pp. 672-679, Atlantic City, NJ, Sep. 28-30, 1999.(with C. Zeng and N.R. Saxena)
  28. "Fault-Tolerance Projects at Stanford CRC," Military and Aerospace Applications of Programmable Devices and Technologies Conference (MAPLD), Laurel, MD, Sep. 28-30, 1999.(with P.P. Shirvani, N.R. Saxena, N. Oh, S. Mitra, S.-Y. Yu, W.-J. Huang, S. Fernandez-Gomez, and N.A. Touba)
  29. "RP-SYN: Synthesis of Random Pattern Testable Circuits with Test Point Insertion," IEEE Trans. CAD., Vol. 18, No. 8, pp. 1202-1213, Aug. 1999. (with N.A. Touba)
  30. "An Output Encoding Problem and a Solution Technique," IEEE Trans. CAD., Vol. 18, No. 6, pp. 761-768, June 1999. (with S. Mitra and L.J. Avra)
  31. " PADded Cache: A New Fault-Tolerance Technique for Cache Memories," 17th IEEE VLSI Test Symposium, pp. 440-445, Dana Point, CA, Apr. 24-29, 1999. (with P.P. Shirvani)
  32. Li, C.-M.J., and E.J. McCluskey, "IDDQ Data Analysis Using Current Signature," 1998 IEEE Int. Workshop on IDDQ Testing, pp. 37-42, San Jose, CA, Nov. 12-14, 1998.
  33. Mitra, S., P.P. Shirvani, and E.J. McCluskey, "Fault Location in FPGA-Based Reconfigurable Systems," IEEE Intl. High Level Design Validation and Test Workshop, pp. 143-150, La Jolla, CA, Nov. 12-14, 1998.
  34. Chang, T.Y.J., C.-W. Tseng, C.-M.J. Li, M. Purtell, and E.J. McCluskey, "Analysis of Pattern-Dependent and Timing-Dep endent Failures in an Experimental Test Chip," Proc. 1998 Int. Test Conf., pp. 184-193, Washington, DC, Oct. 20-22, 1998.
  35. Chang, T.Y.J., and E.J. McCluskey, "Detecting Resistive Shorts for CMOS Domino Circuits," Proc. 1998 Int. Test Conf., pp. 890-899, Washington, DC, Oct. 20-22, 1998.
  36. Saxena, N.R., and E.J. McCluskey, " Dependable Adaptive Computing Systems," IEEE Systems, Man, and Cybernetics Conf., San Diego, CA, pp. 2172-2177, Oct. 11-14, 1998.
  37. Chang, .T.Y.J., C.W. Tseng, Y.C. Chu, S. Wattal, M. Purtell, and E.J. McCluskey, "Experimental Results for IDDQ and VLV Testing," 16th IEEE VLSI Test Symposium, pp. 118-123, Monterey, CA, Apr. 26-30, 1998.
  38. Mitra, S., and E.J. McCluskey, " Output Encoding for Hazard-Free Robust Path Delay Fault Testability," 5th IEEE Intl. Test Synthesis Workshop, Santa Barbara, CA, Mar. 9-11, 1998.
  39. Saxena, N.R., E.J. McCluskey, and L.J. Avra, "Synthesis of Error Correction and Detections Circuits," 5th IEEE Int. Test Synthesis Workshop, Santa Barbara, CA, Mar. 9-11, 1998.
  40. Mitra, S., L. Avra, and E.J. McCluskey, "An Output Encoding problem and a Solution Technique," 1997 Intl. Conf. on Computer-Aided Design, pp. 304-307, San Jose, CA, Nov. 9-13, 1997.
  41. Makar, S.R., and E.J. McCluskey, " IDDQ Test Pattern Generation for Scan Chain Latches and Flip-Flops," 1997 Int. Workshop on IDDQ Testing, pp. 2-6, Washington, DC, Nov. 5-6, 1997.
  42. Mitra, S., L. Avra, and E.J. McCluskey, "Scan Synthesis for One-Hot Signals," Proc. 1997 Int. Test Conf., pp. 714-722, Washington, DC, Nov. 3-5, 1997.
  43. Touba, N.A., and E.J. McCluskey, "Pseudo-Random Pattern Testing of Bridging Faults ", Proc. of IEEE Int. Conference on Computer Design (ICCD), Austin, TX, USA, Oct. 12-15, 1997. (CRC TR 97-2)
  44. Touba, N.A.,and E.J. McCluskey, "LogicSynthesis of Multilevel Circuits with Concurrent Error Detection," IEEE Trans. CAD, Vol. 16, No. 7, pp. 783-789, July 1997.
  45. Mitra, S., L. Avra, and E.J. McCluskey, "Scan Synthesis for One-Hot Signals," 4th IEEE Intl. Test Synthesis Workshop, Santa Barbara, CA, May 5-7, 1997.
  46. Chang, T.Y.J., and E.J. McCluskey, " SHOrt Voltage Elevation (SHOVE) Test for Weak CMOS ICs," 15th IEEE VLSI Test Symposium, pp. 446-451, Monterey, CA, Apr. 27-30, 1997. (CRC TN 96-2)
  47. Makar, S.R., and E.J. McCluskey, " ATPG For Scan Chain Latches and Flip-Flops," 15th IEEE VLSI Test Symposium, pp. 364-369, Monterey, CA, Apr. 27-30, 1997. (CRC TN 96-3)
  48. Norwood, R.B., and E.J. McCluskey, "High-Level Synthesis for Scan," 15th IEEE VLSI Test Symposium, pp. 370-375, Monterey, CA, Apr. 27-30, 1997.
  49. Saxena, N.R., and E.J. McCluskey, "Parallel Signature Analysis Design with Bounds on Aliasing," IEEE Trans. Comput., Vol. 46, No. 4, pp. 425-438, Apr. 1997.
  50. Touba, N.A., and E.J. McCluskey, " Partial Isolation Rings for Testing Embedded Cores," IEEE Int. High Level Design Validation and Test Workshop, Oakland, CA, Nov. 15-16, 1996.
  51. Saxena, N.R., and E.J. McCluskey, "Counting Two-State Transition-Tour Sequences," IEEE Trans. Comput., Vol. 45, No. 11, pp. 1337-1342, Nov. 1996.
  52. Chang, T.Y.J., and E.J. McCluskey, "SHOrt Voltage Elevation (SHOVE) Test," 1996 IEEE Int. Workshop on IDDQ Testing, pp. 45-49, Washington, DC, Oct. 24-25, 1996.
  53. Makar, S.R., and E.J. McCluskey, " Some Faults Need an Iddq Test," 1996 IEEE Int. Workshop on IDDQ Testing, pp. 102-103, Washington, DC, Oct. 24-25, 1996. "(CRC TN 96-1)
  54. Chang, T.Y.J., and E.J. McCluskey, " Detecting Delay Flaws by Very-Low-Voltage Testing," Proc. 1996 Int. Test Conf., pp. 367-376, Washington, DC, Oct. 22-24, 1996.
  55. Franco,P., S. Ma, T.Y.J. Chang, Y. Chu, S. Wattal, R. Stokes, W. Farwell, E.J. McCluskey, "Analysis and Detection of Timing Failures in an Experimental Test Chip," Proc. 1996 Int. Test Conf., pp. 671-700, Washington, DC, Oct. 22-24, 1996.
  56. Norwood, R.B., and E.J. McCluskey, "Orthogonal Scan Path Architectures," Proc. 1996 Int. Test. Conf., pp. 659-668, Washington, DC, Oct. 22-24, 1996.
  57. Touba, N.A., and E.J. McCluskey, " Altering a Pseudo-Random Sequence of Bits for Scan-Based BIST," Proc. 1996 Int. Test. Conf., pp. 167-175, Washington, DC, Oct. 22-24, 1996.
  58. Norwood, R.B., and E.J. McCluskey, "Orthogonal Scan Paths for Data Path Logic," Third Int. Test Synthesis Workshop, Santa Barbara, CA, May 6-8, 1996.
  59. Touba, N.A., and E.J. McCluskey, " Altering a Pseudo-Random Bit Sequence for Mixed-Mode Scan BIST," 3rd Int. Test Synthesis Workshop, Santa Barbara, CA, May 6-8, 1996.
  60. Norwood, R.B., and E.J. McCluskey,"Synthesis-for-Scan and Scan Chain Ordering," 14th IEEE VLSI Test Symp. , pp. 87-92, Princeton, NJ, Apr. 28-May 1, 1996.
  61. Touba, N.A., and E.J. McCluskey,"Test Point Insertion Based on Path Tracing," 14th IEEE VLSI Test Symp., pp. 2-8, Princeton, NJ, Apr. 28-May 1, 1996.
  62. Chang, T.Y.J., and E.J. McCluskey," Quantitative Analysis of Very-Low-Voltage Testing," 14th IEEE VLSI Test Symp., pp. 332-337, Princeton, NJ, Apr. 28-May 1, 1996.
  63. Touba, N.A., and E.J. McCluskey," Applying Two-Pattern Tests Using Scan-Mapping," 14th IEEE VLSI Test Symp., pp. 393-397, Princeton, NJ, Apr. 28-May 1, 1996.
  64. Franco, P., W.D. Farwell, R.L. Stokes, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Chip and Experiment Design," Proc. 1995 Int. Test Conf., pp. 653-662, Washington, D.C., Oct. 23-25, 1995.
  65. Ma, S.C., P. Franco, and E.J. McCluskey, "An Experimental Chip to Evaluate Test Techniques Experiment Results," Proc. 1995 Int. Test Conf., pp. 663-672, Washington, D.C., Oct. 23-25, 1995.
  66. Touba, N.A., and E.J. McCluskey, " Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST," Proc. 1995 Int. Test Conf., pp. 674-682, Washington, D.C., Oct. 23-25, 1995.
  67. Touba, N.A., and E.J. McCluskey, "Synthesis of Mapping Logic for Generating Transformed Pseudo-Random Patterns for BIST," presented at the 2nd Int. Test Synthesis Workshop, Santa Barbara, CA, May 8-10, 1995.
  68. Makar, S., and E.J. McCluskey, "Checking Experiments to Test Latches," 13th IEEE VLSI Test Symp., pp. 196-201, Princeton, NJ, Apr. 30 - May 3, 1995.
  69. Mukund, S.K., E.J. McCluskey, and T.R.N. Rao, "An Apparatus for Pseudo-Deterministic Testing," 13th IEEE VLSI Test Symp., pp. 125-131, Princeton, NJ, Apr. 30 - May 3, 1995.
  70. Touba, N.A., and E.J. McCluskey, " Transformed Pseudo-Random Patterns for BIST," 13th IEEE VLSI Test Symp., pp. 410-416, Princeton, NJ, Apr. 30 - May 3, 1995.
  71. Ma, S.C., and E.J. McCluskey, "Open Faults in BiCMOS Gates," IEEE Trans. Computer-Aided Design, pp. 567-575, May 1995.
  72. Boley, D., G.H. Golub, S. Makar, N. Saxena, and E.J. McCluskey, "Floating Point Fault-Tolerance with Backward Error Assertions," IEEE Trans. Comput., Special Issue on Fault-Tolerant Computing, pp. 302-311, Feb. 1995.
  73. Touba, N.A. and E.J. McCluskey, "Logic Synthesis Techniques for Reduced Area Implementation of Multilevel Circuits with Concurrent Error Detection," Proc. of ACM/IEEE Int. Conference on Computer-Aided Design (ICCAD), pp. 651-654, San Jose, CA, USA, Nov. 6-10, 1994.
  74. Avra, L.J., and E.J. McCluskey, "High-Level Synthesis of Testable Designs: An Overview of University Systems," Proc. 1994 Int. Test Conf., Test Synthesis Seminar, Washington, D.C., TS Paper 1.1, Oct. 2-6, 1994. (CRC TR 94-8)
  75. Touba, N.A. and E.J. McCluskey, "Automated Synthesis of Random Pattern Testable Circuits", Proc. of IEEE Int. Test Conference (ITC), pp. 174-183, Washington, D.C., USA, Oct. 2-6, 1994.
  76. Saxena, N.R., and E.J. McCluskey, "Linear Complexity Assertions for Sorting Algorithms," IEEE Trans. Software Eng., Vol. 20, No. 6, pp. 424-431, June 1994.
  77. Touba, N.A., and E.J. McCluskey, "Logic Synthesis of Random Pattern Testable Circuits Using Algebraic Transformations," First Int. Test Synthesis Workshop, Poster Session, Santa Barbara, CA, May 18-20, 1994.
  78. Franco, P., and E.J. McCluskey, "On Line Delay Testing of Digital Circuits," 12th IEEE VLSI Test Symposium, Cherry Hill, NJ, pp. 167-173, Apr. 25-28, 1994. (CRC TR 94-1)
  79. Franco, P., and E.J. McCluskey, "3-Pattern Delay Fault Tests," 12th IEEE VLSI Test Symposium, Cherry Hill, NJ, pp. 452-456, Apr. 25-28, 1994. (CRC TR 94-1)
  80. Ma, S.C., and E.J. McCluskey, "Open Faults in BiCMOS Gates," 12th IEEE VLSI Test Symposium, Cherry Hill, NJ, pp. 434-439, Apr. 25-28, 1994. (CRC TR 93-4 and CRC TR 94-1)
  81. Hao, H., and E.J. McCluskey, "Analysis of Gate Oxide Shorts in CMOS Circuits," IEEE Trans. Comput., Vol. 42, No. 12, pp. 1510-1516, Dec. 1993.
  82. Avra, L.J., and E.J. McCluskey, "Synthesizing for Scan Dependence in Built-In Self-Testable Designs," Proc. Int. Test Conf., Baltimore, MD, pp. 734-743, Oct. 17-21, 1993.
  83. Hao, H., and E.J. McCluskey, "Very-Low-Voltage Testing for Weak CMOS Logic IC's," Proc. 1993 Int. Test Conf., Baltimore, MD, pp. 275-284, Oct. 17-21, 1993. (CRC TR 93-1 and CRC TR 93-2)
  84. McCluskey, E.J., "Quality and Single-Stuck Faults," Proc. 1993 Int. Test Conf., Baltimore, MD, p. 597, Oct. 17-21, 1993. (CRC TR 93-2)
  85. Furuya, K., and E.J. McCluskey, "Two-Pattern Test Capabilities of Autonomous TPG Circuits," Trans. on Information and Systems of IEICE, Vol. E76-D, No. 7, pp. 800-808, July 1993.
  86. McCluskey, E.J., "Logic Design," in Reference Data for Engineers: Radio, Electronics, Computer, and Communications, 8th Ed., Chapter 43, Van Valkenburg, ed., Howard W. Sams & Co., Inc., Indianapolis, 1993.
  87. McCluskey, E.J., "Logic Design," in Encyclopedia of Computer Science and Engineering, 3rd Ed., Anthony Ralston and Edwin D. Reilly, eds., Van Nostrand Reinhold, New York, pp. 775-778, 1993.
  88. McCluskey, E.J., "Switching Theory," in Encyclopedia of Computer Science and Engineering, 3rd Ed., Anthony Ralston and Edwin D. Reilly, eds., Van Nostrand Reinhold, New York, pp. 1332-1336, 1993.
  89. Furuya, K., S. Seki, and E.J. McCluskey, "Synthesis of Autonomous TPG Circuits Oriented for Two-Pattern Testing," 1st Asian Test Symposium, Hiroshima, Japan, pp. 235-240, Nov. 26-27, 1992.
  90. Furuya, K., and E.J. McCluskey, "A Method and the Effect of Shuffling Compactor Inputs in VLSI Self-Testing," Special Issue on PRFTS, Trans. on Information and Systems of IEICE, pp. 842-846, Nov. 1992.
  91. Ma, S.C., and E.J. McCluskey, "Non-Conventional Faults in BiCMOS Digital Circuits," ITC92, pp. 882-891, Sep. 20-24, 1992. (CRC TR 92-2)
  92. Saxena, N.R., P. Franco, and E.J. McCluskey, "Simple Bounds on Signature Analysis Aliasing for Random Testing," Special Issue on Fault-Tolerant Computing, IEEE Trans. Comput, pp. 638-645, May 1992.
  93. Hao, H., and E.J. McCluskey, "On the Modeling and Testing of Gate Oxide Shorts in CMOS Logic Gates," 1991 IEEE International Workshop on Defect and Fault Tolerance in VLSI Systems, Hidden Valley, PA, pp. 161-174, Nov. 18-20, 1991. (CRC TR 91-6)
  94. Furuya, K., and E.J. McCluskey, "Two-Pattern Test Capabilities of Autonomous TPG Circuits," ITC91, pp. 704-711, Oct. 29 - Nov. 1, 1991. (CRC TR 91-5)
  95. Avra, L., "Allocation and Assignment in High-Level Synthesis for Self-Testable Data Paths," ITC91, pp. 463-472, Oct. 29 - Nov. 1, 1991. (CRC TR 90-9 & 91-5)
  96. Franco, P., and E.J. McCluskey, "Delay Testing of Digital Circuits By Output Waveform Analysis," ITC91, pp. 798-807, Oct. 29 - Nov. 1, 1991. (CRC TR 91-5)
  97. Saxena, N.R., E.J. McCluskey, and P. Franco, "Refined Bounds on Signature Analysis Aliasing for Random Testing," ITC91, pp. 818-827, Oct. 29 - Nov. 1, 1991. (CRC TR 91-5)
  98. Millman, S., and E.J. McCluskey, "Bridging, Transition, and Stuck-Open Faults in Self-Testing CMOS Checkers," FTCS-21, pp. 154-161, June 25-27, 1991. (CRC TR 89-6 & 91-5)
  99. Saxena, N.R., and E.J. McCluskey, "Bounds on Signature Analysis Aliasing for Random Testing," FTCS-21, pp. 104-111, June 25-27, 1991. (CRC TR 91-4)
  100. Franco, P., N. Saxena, and E.J. McCluskey, "Relating Aliasing in Signature Analysis to Test Length and Register Design," ISCAS'91, pp. 1889-1892, June 11-14, 1991. (CRC TR 91-4)
  101. McCluskey, E.J., "Techniques for Test Output Response Analysis," ISCAS'91, pp. 1869-1872, June 11-14, 1991. (CRC TR 91-4)
  102. McCluskey, E.J., "Who Needs Design for Testability?," Dig. 1991 IEEE Int. Solid-State Circuits Conf., San Francisco, CA, Feb. 13-15, 1991. (CRC TR 90-8)
  103. McCluskey, E.J., "Half a century of Logic Synthesis," EURO ASIC 90, Paris, France, May 29-31, 1990; in Logic and Architecture Synthesis, pp. 3-8, P. Michel and G. Saucier, ed. North-Holland, 1991. (CRC TR 90-4)
  104. Millman, S.D., E.J. McCluskey, and J.M. Acken, "Diagnosing CMOS Bridging Faults with Stuck-At Fault Dictionaries," ITC90, pp. 860-870, Sep. 10-12, 1990.
  105. Saxena, N.R., and E.J. McCluskey, "Bounds on Aliasing Probabilities under Bernoulli Error Model for Signature Analysis," ITC90, Poster Session. Sep. 10-12, 1990.
  106. Norman, R.H., and E.J. McCluskey, "Design for Integrity," Advanced Microelectronics Technology Qualification, Reliability and Logistics Workshop, San Diego, CA, Aug. 28-30, 1990.
  107. McCluskey, E.J., "Design for Test Overview," Microelectronic System Education Conference & Exposition, San Jose, CA, July 29 - Aug. 1, 1990.
  108. McCluskey, E.J., "Design Techniques for Testable Embedded Error Checkers," Special Issue on Fault-Tolerant Systems, Computer, pp. 84-88, July 1990.
  109. Saxena, N.R., and E.J. McCluskey, "Analysis of Checksums, Extended-Precision Checksums and Cyclic Redundancy Checks," IEEE Trans. Comput., Vol. 39, No. 7, pp. 969-975, July 1990. ( CRC TR 88-9)
  110. Saxena, N.R., and E.J. McCluskey, "Control-Flow Checking Using Watchdog Assists and Extended-Precision Checksums," FTCS-19, pp. 428-435; IEEE Trans. Comput., Vol. 39, No. 4, pp. 554-559, Apr. 1990. (CRC TR 89-2)
  111. Avra, L., and E.J. McCluskey, "Behavioral Synthesis of Testable Systems with VHDL," COMPCON90, pp. 410-415, Feb. 26 - Mar. 2, 1990. (CRC TR 89-10)
  112. McCluskey, E.J.,"Foreword" in Structured Logic Testing, Prentice-Hall Inc., Englewood Cliffs, NJ, 1990.
  113. Boley, D., G.H. Golub, S. Makar, N. Saxena, and E.J. McCluskey, "Backward Error Assertions for Checking Solutions to Systems of Linear Equations," Numerical Analysis Project, Manuscript NA-89-12, Nov. 1989.
  114. Makar, S., and E.J. McCluskey, "The Critical Path for Multiple Faults," 1989 IEEE Int. Conf. on Computer-Aided Design, Santa Clara, CA, pp. 162-165, Nov. 6-9, 1989. (CRC TR 89-3)
  115. Saxena, N.R., and E.J. McCluskey, "Arithmetic and Galois Checksums," ICCAD89, pp. 570-573, Nov. 6-9, 1989. (CRC TR 89-3)
  116. Mourad, S., M. Martonosi, and E.J. McCluskey, "Benchmarking Magnitude Comparators," Fourth Technical Workshop: New Directions for IC Testing, Victoria, B.C., Canada, Oct. 24-26, 1989.
  117. Mourad, S., and E.J. McCluskey, "Fault Analysis Using Signature Analyzers," 1989 International Conference on Circuits and Systems, Nanjing, China, July 6-9, 1989. (CRC TR 89-3)
  118. Udell, J.G. Jr., and E.J. McCluskey, "Pseudoexhaustive Test and Segmentation; Formal Definitions and Extended Fault Coverage Results," FTCS-19, pp. 292-298, June 21-23, 1989. (CRC TR 89-2)
  119. Millman, S.D., and E.J. McCluskey, "Detecting Stuck-Open Faults with Stuck-At Test Sets," IEEE Custom Integrated Circuits Conference, San Diego, CA, May 15-18, 1989. (CRC TR 89-2 & 89-5)
  120. McCluskey, E.J., and F. Buelow, "IC Quality and Test Transparency," ITC88, pp. 295-301; IEEE Trans. on Industrial Electronics, Vol. 36, No. 2, pp. 197-202, May 1989.
  121. Mourad, S., and E.J. McCluskey, "Testability of Parity Checkers," IEEE Trans. on Industrial Electronics, Vol. 36, No. 2, pp. 254-262, May 1989.
  122. Wang, L.-T., M. Marhoefer, and E.J. McCluskey, "A Self-Test and Self-Diagnosis Architecture for Boards Using Boundary Scans," European Test Conference, Paris, France, pp. 119-126, Apr. 12-14, 1989. (CRC TR 89-2)
  123. Lau, C., C.M. Hu, and E.J. McCluskey, "Research in Advanced Electronic System Reliability," Naval Research Reviews, Vol. XLI, pp. 9-19, Three/1989.
  124. Wang, L.-T., and E.J. McCluskey, "Linear Feedback Shift Register Design Using Cyclic Codes," IEEE Trans. Comput., Vol. 37, No. 10, pp. 1302-1306 Oct. 1988.
  125. Wang, L.-T., and E.J. McCluskey, "Circuits for Pseudo-Exhaustive Test Pattern Generation Using Cyclic Codes," IEEE Trans. CAD, Vol 7, No. 10, pp. 1068-1080, Oct. 1988.
  126. Makar, S.R., and E.J. McCluskey, "On The Testing Of Multiplexers," ITC88, pp. 669-679, Sep. 12-14, 1988. (CRC TR 88-5)
  127. McCluskey, E.J., "Practice and Theory," ITC88, pp. 203-204, Sep. 12-14, 1988. (CRC TR88-5)
  128. Millman, S.D., and E.J. McCluskey, "Detecting Bridging Faults With Stuck-at Test Sets," ITC88, pp. 773-783, Sep. 12-14, 1988. (CRC TR 87-20 & 88-5)
  129. Mourad, S., and E.J. McCluskey, "On Benchmarking Digital Testing Systems," ITC88, Poster Session, pp. 997, Sep. 12-14, 1988. (CRC TR 88-5)
  130. Udell, J.G. Jr., "Reconfigurable Hardware for Pseudo-Exhaustive Test," ITC88, pp. 522-530, Sep. 12-14, 1988. (CRC TR 87-4 & 88-5)
  131. Udell, J.G. Jr., and E.J. McCluskey, "Partial Hardware Partitioning: A New Pseudo-Exhaustive Test Implementation," ITC88, Poster Session, pp. 1000, Sep. 12-14, 1988. (CRC TR 88-5 & 88-7)
  132. Nanya, T., S. Mourad, and E.J. McCluskey, "Multiple Stuck-at Fault Testability of Self-testing Checkers,"FTCS-18, pp. 381-386, June 27-30, 1988. (CRC TR 88-5)
  133. Mahmood, A., and E.J. McCluskey, "Concurrent Error Detection Using Watchdog Processors - A Survey," IEEE Trans. Comput., Vol. 37, No. 2, pp. 160-174, Feb. 1988. (CRC TR 85-7)
  134. Liu, D.L., and E.J. McCluskey, "Design of Large Embedded CMOS PLA's for Built-In Self-Test," IEEE Trans. CAD, Vol. 7, No. 1, pp. 50-59, Jan. 1988.
  135. McCluskey, E.J., S. Makar, S. Mourad, and K.D. Wagner, "Probability Models for Pseudorandom Test Sequences," IEEE Trans. CAD, Vol. 7, No. 1, pp. 68-74, Jan. 1988.
  136. Wang, L.-T., and E.J. McCluskey, "Hybrid Designs Generating Maximum Length Sequences," IEEE Trans. CAD, Vol. 7, No. 1, pp. 91-99, Jan. 1988.
  137. Mourad, S., and E.J. McCluskey, "Fault Models," in Testing and Diagnosis of VLSI and ULSI, pp. 49-68, Kluwer Academic Publishers, 1988.
  138. Udell, J.G. Jr., and E.J. McCluskey, "Efficient Circuit Segmentation for Pseudo-Exhaustive Test," ICCAD87, pp. 148-151, Nov. 9-12, 1987.
  139. Amer, H.H., M.L. Côrtes, and E.J. McCluskey, "Robust Dynamic Recovery Mechanisms," Proc., Int'l. Conf. Computer Design, Port Chester, NY, pp. 310-313, Oct. 1987.
  140. Liu, D.L., and E.J. McCluskey, "CMOS Scan-Path IC Design for Stuck-Open Fault Testability," IEEE Journ. Solid State Circuits, Vol. SC-22, No. 5, pp. 880-85, Oct. 1987. (CRC TR 87-10)
  141. Liu, D.L., and E.J. McCluskey, "Design of Large Embedded CMOS PLA for Built-In Self-Test," Proc., Int. Conf. on Comput. Design, Port Chester, NY, pp. 678-681, Oct. 1987.
  142. Wang, L.-T., and E.J. McCluskey, "Circuits for Pseudo-Exhaustive Test Pattern Generation Using Shortened Cyclic Codes," IEEE 1987 Int. Conference on Comput. Design: VLSI In Computers & Processors (ICCD-87), Port Chester, NY, pp. 450-453, Oct. 1987.
  143. McCluskey, E.J., S. Mourad, and K.D. Wagner, "Probability Models for Pseudorandom Test Sequences," ITC87, pp. 471-479, Sep. 1-3, 1987. (CRC TR 87-12)
  144. Shperling, I., and E.J. McCluskey, "Circuit Segmentation for Pseudo-Exhaustive Testing via Simulated Annealing," ITC87, pp. 58-65, Sep. 1-3, 1987. (CRC TR 87-2 & 87-12)
  145. Wang, L.-T., and E.J. McCluskey, "Built-In Self-Test for Sequential Machines," ITC87, pp. 334-41, Sep. 1-3, 1987. (CRC TR 87-12)
  146. Liu, D.L., and E.J. McCluskey, "Designing CMOS Combinational Circuits for Switch-level Testability," IEEE Design & Test of Comput., pp. 42-49, Aug. 1987. (CRC TR 87-9)
  147. Saxena, N.R., and E.J. McCluskey, "Extended Precision Checksums," FTCS-17, pp. 142-147, July 6-8, 1987.
  148. Wang, L.-T., and E.J. McCluskey and S. Mourad, "Shift Register Testing of Sequential Machines," FTCS-17, pp. 66-71, July 6-8, 1987.
  149. McCluskey, E.J., "Exhaustive and Pseudo-Exhaustive Testing," CRC TR 87-13, July 1987.
  150. Amer, H.H., and E.J. McCluskey, "Calculation of Coverage Parameter," IEEE Trans. Reliability, Spec. Issue on Fault Tolerant Comput.,Vol. R-36, No. 2, pp. 194-198, June 1987.
  151. Liu, D., and E.J. McCluskey, "Design of CMOS VLSI Circuits for Testability," CICC'86, pp. 421-424; Journ. of Semicustom IC's, Vol. 4, No. 4, pp. 5-10, June 1987. (CRC TR 86-1)
  152. Mourad, S., J.L.A. Hughes, and E.J. McCluskey, "Effectiveness of Single Stuck-at Fault Tests in Detecting Multiple Faults," Int. Journ. of Comput. and Math. Appl., Vol. 13, pp. 455-459, May/June 1987.
  153. Liu, D.L., and E.J. McCluskey, "A CMOS PLA Design for Built-In Self-Test," Proc., 1987 IEEE Int. Symp. on Circuits and Syst., Philadelphia, PA, pp. 859-862, May 1987. (CRC TR 87-5)
  154. Liu, D.L., and E.J. McCluskey, "High Fault Coverage Self-Test Structures for CMOS ICs," Proc., 1987 IEEE Custom Integrated Circuits Conf., Portland, OR, pp. 68-71, May 1987. (CRC TR 87-5)
  155. Liu, D.L., and E.J. McCluskey, "A CMOS Cell Library Design for Testability," VLSI Systems Design, pp. 58-65, May 1987.
  156. Wagner, K.D., C.K. Chin, and E.J. McCluskey, "Pseudorandom Testing," IEEE Trans. Comput., Vol. C-36, No. 3, pp. 332-343, Mar. 1987.
  157. Amer, H.H., and E.J. McCluskey, "Latent Failures and Coverage in Fault-Tolerant Systems," Proc. Phoenix Conf. Comput. and Comm., Scottsdale, AZ, pp. 89-93, Feb. 1987.
  158. Amer, H.H., and E.J. McCluskey, "Modeling the Effect of Chip Failures on Cache Memory Systems," Proc. Third Int. Conf. Data Eng., Los Angeles, CA, pp. 340-346, Feb. 1987.
  159. Chin, C. K., and E.J. McCluskey, "Test Length for Pseudorandom Testing," ITC85, pp. 94-99; IEEE Trans. Comput., Vol. C-36, No. 2, pp. 252-256, Feb. 1987. (CRC TR 85-11 & 85-14)
  160. Liu, D.L., and E.J. McCluskey, "A VLSI CMOS Circuit Design Technique to Aid Test Generation," Proc., 1987 Phoenix Conf. Comput. and Comm., Scottsdale, AZ, pp. 116-120, Feb. 1987. (CRC TR 86-18)
  161. McCluskey, E.J., "Computer Society has it Backwards," IEEE Design and Test, pp. 6-7, Feb. 1987.
  162. Amer, H.H., and E.J. McCluskey, "Weighted Coverage in Fault-Tolerant Systems," Proc. Reliability and Maintainability Symp., RAMS-87, Philadelphia, PA, pp. 187-191, Jan. 1987. (CRC TR 87-8)
  163. McCluskey, E.J., and S. Mourad, "Comparing Causes of IC Failures," . Perspectives in Computing, Vol. 18, Developments in Integrated Circuit Testing, D.M. Miller, ed., Academic Press Limited, pp. 13-46, 1987. (CRC TR 86-2)
  164. McCluskey, E.J., "Comparing Causes of System Failure," Microprocessing and Microprogramming 18, North-Holland, pp. 11-22, 1987.
  165. McCluskey, E.J., "Reliable Digital Systems and Related Stanford University Research," The Evolution of Fault-Tolerant Computing, Springer-Verlag Wien, Austria, pp. 215-250, 1987.
  166. Wang, L.-T., and E.J. McCluskey, "Feedback Shift Registers for Self-Testing Circuits," VLSI Systems Design, pp. 50-58, Dec. 1986.
  167. Wagner, K.D., C.K. Chin, and E.J. McCluskey, "Fault Coverage of Pseudorandom Testing," ICCAD86, pp. 48-51, Nov. 11-13, 1986. (CRC TR 86-14)
  168. Wang, L.-T, and E.J. McCluskey, "Complete Feedback Shift Register Design for Built-In Self-Test," ICCAD86, pp. 56-59, Nov. 11-13, 1986.(CRC TR 86-14 & 86-17)
  169. McCluskey, E.J., "VLSI Technology Research at Stanford," 20th IBM Computer Science Symposium, Japan, Oct. 10-12, 1986. (CRC TR 86-13)
  170. McCluskey, E.J., "Testing Futures," Test Technology Workshop, Washington, D.C., Sep. 11, 1986. (CRC TR 86-12)
  171. Cortes, M.L., and E.J. McCluskey, "An Experiment on Intermittent-Failure Mechanisms," ITC86, Sep. 8-11, 1986. (CRC TR 86-5)
  172. Freeman, G.G., D.L. Liu, B. Wooley, and E.J. McCluskey, "Two CMOS Metastability Sensors," ITC86, Sep. 8-11, 1986. (CRC TR 86-5)
  173. Hughes, J.L.A., and E.J. McCluskey, "Multiple Stuck-At Fault Coverage of Single Stuck-At Fault Test Sets,"ITC86, Sep. 8-11, 1986. (CRC TR 86-5)
  174. Wang, L.-T., and E.J. McCluskey, "Circuits for Pseudo-Exhaustive Test Pattern Generation," ITC86, pp. 25-37, Sep. 8-11, 1986. (CRC TR 86-5)
  175. Wang, L.-T., and E.J. McCluskey, "A Hybrid Design of Maximum-Length Sequence Generators," ITC86, pp. 38-47, Sep. 8-11, 1986. (CRC TR 86-5)
  176. McCluskey, E.J., "Hardware Fault Tolerance," Sixteenth Annual Institute in Computer Science, University of California at Santa Cruz, Aug. 25, 1986. (CRC TR 86-11)
  177. Amer, H.H., and E.J. McCluskey, "Calculation of the Coverage Parameter for the Reliability Modeling of Fault-Tolerant Computer Systems," ISCAS'86, pp. 1050-1053, May 5-7, 1986. (CRC TR 86-1)
  178. Cortes, M.L., E.J. McCluskey, K.D. Wagner, and D.J. Lu, "Properties of Transient Errors Due to Power Supply Disturbances," IEEE Int'l Conf. on Circuits and Systems, San Jose, CA, May 5-7, 1986.
  179. Wang, L.-T., and E.J. McCluskey, "Concurrent Built-In Logic Block Observer (CBILBO)," ISCAS'86, pp. 1054-1057, May 5-7, 1986. (CRC TR 86-1)
  180. McCluskey, E.J., "A Comparison of Test Pattern Generation Techniques,"Proc. of Fault-Tolerant Systems and Diagnostics, pp. 11-20, Brno, Czechoslovakia, June 1986.
  181. Mourad, S., J. A. Hughes, and E.J. McCluskey, "Stuck-At Fault Detection in Parity Trees," Proc. of Fault-Tolerant Systems and Diagnostics (FTSD-9), pp. 142-147, Brno, Czechoslovakia, June 1986; FJCC, Dallas, TX, pp. 836-840, Nov. 1986. (CRC TR 85-23 & 86-7)
  182. Bozorgui-Nesbat, S., and E.J. McCluskey, "Lower Overhead Design for Testability of Programmable Logic Arrays," ITC84, pp. 856-865; IEEE Trans. Comput., Vol. C-35, No. 4, pp. 379-383, Apr. 1986.
  183. Wang, L.-T., and E.J. McCluskey, "Condensed Linear Feedback Shift Register (LFSR) Testing -- A Pseudo-Exhaustive Test Technique, " IEEE Trans. Comput., Vol. C-35, No. 4, pp. 367-370, Apr. 1986. (CRC TR 85-24)
  184. Mourad, S., J.L.A. Hughes, and E.J. McCluskey, "Multiple Fault Detection in Parity Trees," COMPCON86, pp. 441-444, Mar. 1986.
  185. Cortes, M.L., E.J. McCluskey, K.D. Wagner, and D.J. Lu, "Modeling Power-Supply Disturbances in Digital Circuit," IEEE Int'l Solid-State Circuits Conf., (ISSCC'86), pp. 164-165, Feb. 19-21, 1986.
  186. McCluskey, E.J., "Reliable Digital Systems and Related Stanford University Research," in "Dependable Computing and Fault-Tolerant Systems," Vol. 1, "The Evolution of Fault-Tolerant Computing," Proc. of a 1-Day-Symposium in the honor of William C. Carter, A. Avizienis, H. Kopetz, and J.C. Laprie, eds., Springer-Verlag Wien, New York, pp. 215-250, 1986.
  187. Mahmood, A., A. Ersoz, and E.J. McCluskey, "Concurrent System-Level Error Detection Using a Watchdog Processor," ITC85, pp. 145-152, Nov. 19-21, 1985. (CRC TR 85-11)
  188. McCluskey, E.J., "Test Teaching," ITC85, pp. 235, Nov. 19-21, 1985. (CRC TR 85-11)
  189. Wagner, K.D., and E.J. McCluskey, "Effect of Supply Voltage on Circuit Propagation Delay and Test Applications," Proc., IEEE Int'l Conf. on Computer-Aided Design, Santa Clara, CA, pp. 42-44, Nov. 18-21, 1985. (CRC TR 85-17)
  190. McCluskey, E.J., "Testing Semi-Custom Logic," Semiconductor International, pp. 118-123, Sep. 1985.
  191. Wang, L.-T., and E.J. McCluskey, "Built-In Self Test for Random Logic," Proc., 1985 Int'l Symposium on Circuits and Systems, Vol. 3, Kyoto, Japan, pp. 1305-1308, June 5-7, 1985. (CRC TR 85-5)
  192. McCluskey, E.J., "Built-In Self-Test Techniques," IEEE Design & Test of Computers, pp. 21-28, Apr. 1985.
  193. McCluskey, E.J., "Built-In Self-Test Structures," IEEE Design & Test of Computers, pp. 29-36, Apr. 1985.
  194. Hughes, J.L.A., S. Mourad, and E.J. McCluskey, "An Experimental Study Comparing 74LS181 Test Sets," COMPCON85, pp. 384-387, San Francisco, CA, Feb. 26-28, 1985.
  195. McCluskey, E.J., "Hardware Fault Tolerance," COMPCON85, pp. 260-263, San Francisco, CA, Feb. 26-28, 1985. (CRC TR 84-13)
  196. McCluskey, E.J., "Testable IC Design," Proc., Automated Design and Engineering for Electronics (ADEE) Conf., pp. 252-260, Anaheim, CA, Feb. 26-28, 1985. (CRC TR 85-2)
  197. Khakbaz, J., and E.J. McCluskey, "Concurrent Error Detection and Testing for Large PLA's," DIGITAL VLSI SYSTEMS, M.I. Elmasry, ed., pp. 494-502, IEEE Press, New York, 1985.
  198. McCluskey, E.J., "Logic Design," Reference Data for Engineers: Radio, Electronics, Computer, and Communications, Seventh Ed., Chapter 43, Howard W. Sams & Co., Inc., Indianapolis, 1985.
  199. McCluskey, E.J., "Synchronous Digital Logic," HICSS-18, Vol. 1, pp. 52-63, Jan. 2-4, 1985. (CRC TR 84-12)
  200. Mahmood, A., D.M. Andrews, and E.J. McCluskey, "Executable Assertions and Flight Software," AIAA/IEEE Digital Avionics Systems Conf. (DASC), pp. 346-351, Baltimore, MD, Dec. 3-6, 1984.
  201. McCluskey, E.J., "A Survey of Design for Testability Scan Techniques," VLSI Design, Vol. V, No. 12, pp. 38-61, Dec. 1984.
  202. Bozorgui-Nesbat, S., and E.J. McCluskey, "Design for Delay Testing of Programmable Logic Arrays," ICCAD84, pp. 146-148, Santa Clara, CA, Nov. 12-15, 1984. (CRC TR 84-10)
  203. Hassan, S., and E.J. McCluskey, "Enhancing the Effectiveness of Parallel Signature Analyzers," ICCAD84, pp. 102-104, Santa Clara, CA, Nov. 12-15, 1984.
  204. Mahmood, A., D.M. Andrews, and E.J. McCluskey, "Writing Executable Assertions to Test Flight Software," Eighteenth Annual Asilomar Conference on Circuits, Systems, and Computers, Pacific Grove, CA, pp. 262-266, Nov. 5-7, 1984. (CRC TR 84-14)
  205. McCluskey, E.J., "Testing Semi-Custom Logic," Wescon/84, Anaheim, CA, paper 31/4, Oct. 30 - Nov. 2, 1984. (CRC TR 84-9)
  206. Bozorgui-Nesbat, S., and E.J. McCluskey, "Lower Overhead Design for Testability of Programmable Logic Arrays," ITC84, pp. 856-865, Philadelphia, PA, Oct. 15-18, 1984.
  207. Hassan, S., and E.J. McCluskey, "Pseudo-Exhaustive Testing of Sequential Machines Using Signature Analysis," ITC84, pp. 320-326, Philadelphia, PA, Oct. 15-18, 1984.
  208. Hughes, J.L.A., and E.J. McCluskey, "An Analysis of the Multiple Fault Detection Capabilities of Single Stuck-At Fault Test Sets," ITC84, pp. 52-58, Philadelphia, PA, Oct. 15-18, 1984.
  209. McCluskey, E.J., "Errors in Education," Panel Statement, Academic Curriculum Forum, ITC84, p. 3, Philadelphia, PA, Oct. 15-18, 1984. (CRC TR 84-8)
  210. McCluskey, E.J., "Built-In Self Test Architectures," Academic Curriculum Forum, ITC84, pp. 4-6, Philadelphia, PA, Oct. 15-18, 1984. (CRC TR 84-8)
  211. McCluskey, E.J., "VLSI Design for Testability," 1984 Symposium on VLSI Technology, San Diego, CA, pp. 2-5, Sep. 10-12, 1984; DASC, pp. 523-530 (CRC TR 84-4 & 84-11)
  212. Khakbaz, J., "A Testable PLA Design with Low Overhead and High Fault Coverage," FTCS-13, pp. 426-429, IEEE Trans. Comput., Vol. C-33, No. 8, pp. 743-745, Aug. 1984.
  213. Khakbaz, J., and E.J. McCluskey, "Self-testing Embedded Parity Checkers," IEEE Trans. Comput., Vol. C-33, No. 8, pp. 753-756, Aug. 1984.
  214. Archambeau, E.C., and E.J. McCluskey, "Fault Coverage of Pseudo-Exhaustive Testing," FTCS-14, pp. 141-145, Kissimmee, FL, June 20-22, 1984.
  215. Hassan, S.Z., and E.J. McCluskey, "Increased Fault Coverage Through Multiple Signatures," FTCS-14, pp. 354-359, Kissimmee, FL, June 20-22, 1984.
  216. Wang, L.-T., and E.J. McCluskey, "A New Condensed Linear Feedback Shift Register Design for VLSI/System Testing," FTCS-14, pp. 360-365, Kissimmee, FL, June 20-22, 1984. (CRC TR 84-2)
  217. Hughes, J.L.A., E.J. McCluskey, and D.J. Lu, "Design of Totally Self-Checking Comparators with an Arbitrary Number of Inputs," IEEE Trans. Comput., Vol. C-33, no. 6, pp. 546-550, June 1984. (CRC TR 83-3)
  218. McCluskey, E.J., "Pseudo-Exhaustive Testing for VLSI Devices" ATE Silicon Valley Conf., San Mateo, CA, pp. IV-5 - IV-21, Apr. 10-12, 1984. (CRC TR 84-6)
  219. Lu, D.J., and E.J. McCluskey, "Quantitative Evaluation of Self-Checking Circuits," IEEE Trans. Computer-Aided Design, CAD-3, No. 2, pp. 150-155, Apr. 1984.
  220. McCluskey, E.J., "Verification Testing-A Pseudoexhaustive Test Technique," IEEE Trans. Comput., Vol. C-33, No. 6, pp. 541-546, June 1984. (CRC TR 83-8)
  221. Lu, D.J., and E.J. McCluskey, "Recurrent Test Patterns," ITC83, pp. 76-82, Philadelphia, PA, Oct. 18-20, 1983. (CRC TR 83-10)
  222. Mahmood, A., E.J. McCluskey, and D.J. Lu, "Concurrent Fault Detection Using a Watchdog Processor and Assertions," ITC83, pp. 622-628, Philadelphia, PA, Oct. 18-20, 1983. (CRC TR 83-10 & 83-16)
  223. McCluskey, E.J., "Teaching Testing," ITC83, pp. 163-167, Philadelphia, PA, Oct. 18-20, 1983. (CRC TR 83-10)
  224. McCluskey, E.J., "Exhaustive and Pseudo-exhaustive Test," Built-in Test--Concepts and Techniques, Tutorial, ITC83, Philadelphia, PA, Oct. 18-20, 1983. (CRC TR 83-15)
  225. Xu, X., and E.J. McCluskey, "Test Generation and Fault Diagnosis for Multiple Faults in Combinational Circuits," FTCS-13, pp. 110-113, June 28-30, 1983. (CRC TR 83-2)
  226. McCluskey, E.J., "Design for Testability Survey," Proc., Bias Microelettronica, Sec. 4, pp. 1-9, Milan, Italy, Feb. 23-25, 1983.
  227. McCluskey, E.J., "Logic Design," in Encyclopedia of Computer Science and Engineering, A. Ralston & E.D. Reilly, Jr., Eds., Van Nostrand Reinhold Co., New York, NY, pp. 879-882, 1983.
  228. McCluskey, E.J., "Built-in Verification Test," ITC82, pp. 183-190, Nov. 16-18, 1982. (CRC TR 82-12)
  229. Iyer, R.K., S.E. Butner, and E.J. McCluskey, "A Statistical Failure/Load Relationship: Results of a Multicomputer Study," IEEE Trans. Comput., Vol. C-31, No. 7, pp. 697-706, July 1982.
  230. Namjoo, M., and E.J. McCluskey, "Watchdog Processors and Capability Checking," FTCS-12, June 22-24, 1982. (CRC TR 82-3)
  231. McCluskey, E.J., "Test Questions," (Keynote Address), FTCS-12, p. 43, June 22-24, 1982. (CRC TR 82-3)
  232. McCluskey, E.J., "Verification Testing," Proc., 19th Design Automation Conf., Las Vegas, NV, pp. 495-500, June 14-16, 1982. (CRC TR 81-7)
  233. McCluskey, E.J., "A Discussion of Multiple-Valued Logic Circuits," Proc., 12th Int'l Symposium on Multiple-Valued Logic, Paris, France, pp. 200-205, May 25-27, 1982.
  234. Khakbaz, J., and E.J. McCluskey, "Concurrent Error Detection and Testing for Large PLA's," Joint Special Issue on VLSI, IEEE Trans. on Electron Devices, pp. 756-764 and IEEE J. of Solid-State Circuits, pp. 386-394, Apr. 1982. (CRC TR 81-14)
  235. McCluskey, E.J., "Fault Tolerant Systems," Journal, Information Processing Society in Japan, Vol. 23, No. 4, pp. 378-385, Apr. 1982. (CRC TR 82-1)
  236. McCluskey, E.J., and S. Bozorgui-Nesbat, "Design for Autonomous Test," Tutorial, VLSI, COMPCON82, pp. 290-296, Feb. 1982. (CRC TR 81-1)
  237. McCluskey, E.J., and S. Bozorgui-Nesbat, "Design for Autonomous Test," IEEE Trans. Comput., pp. 866-875, Nov. 1981.
  238. McCluskey, E.J., and J.F. Wakerly, "A Circuit For Detecting and Analyzing Temporary Failures," COMPCON81, pp. 317-321, Feb. 23-26, 1981. (CSL TN 178)
  239. Lu, D.J., E.J. McCluskey, and M. Namjoo, "Summary of Structural Integrity Checking," Proc., Distributed Data Acquisition, Computing, and Control Symposium, pp. 107-109, Miami Beach, FL, Dec. 3-5, 1980. (CSL TN 181)
  240. McCluskey, E.J., "Reliable Computing Systems" Proc., International Computer Symposium 1980, pp. 714-723, Taipei, Republic of China, Dec. 16-18, 1980. (CSL TN 182)
  241. McCluskey, E.J., and S. Bozorgui-Nesbat, "Design for Autonomous Test," Proc., 1980 Test Conf., Philadelphia, PA, pp. 11-13, Nov. 11-13, 1980. (CRC TR 81-1) (CSL TN 180)
  242. Bozorgui-Nesbat, S., and E.J. McCluskey, "Structured Design for Testability to Eliminate Test Pattern Generation," FTCS-10, Kyoto, Japan, pp. 158-163, October 1-3, 1980.
  243. McCluskey, E.J., "Logic Design of MOS Ternary Logic," Proc., Tenth Annual International Symposium on Multiple-Valued Logic, pp. 1-5, Evanston, IL, June 3-5, 1980.
  244. Hayes, J.P., and E.J. McCluskey, "Testability Considerations in Microprocessor-Based Design," Computer, pp. 7-26, Mar. 1980. (CSL TR 179)
  245. McCluskey, E.J., and Hayes, J.P., "Testability Considerations in Microprocessor-Based Design," Tutorial: Microcomputer System Software and Languages, Belton E. Allen, editor, 1980 IEEE Catalog No. EHO 174-3, Library of Congress No. 80-84352.
  246. McCluskey, E.J., "Designing with PLA's," Thirteenth Asilomar Conf. on Circuits, Systems and Computers, pp. 442-445, Pacific Grove, CA, Nov. 5-7, 1979. (CSL TN 168)
  247. McCluskey, E.J., "Testing and Diagnosis of Logic," Proc., Euro/IFIP 79, pp. 735-738, London, England, Sep. 25-28, 1979.
  248. McCluskey, E.J., "Logic Design of Multi-Input Quad I2L Circuits," Proc., Ninth Int'l Symposium on Multiple-Valued Logic, pp. 121-127, Bath, England, May 29-31, 1979.
  249. McCluskey, E.J., "Design for Maintainability and Testability," Proc., Government Microcircuit Applications Conference, pp. 44-47, Monterey, CA, Nov. 14-16, 1978. (CSL TN 145)
  250. McCluskey, E.J., "Logic Design of Multi-Valued I2L Logic Circuits," Proc., Eight Int'l Symposium on Multiple-valued Logic, Chicago, IL, pp. 14-22, May 24-26, 1978; IEEE Trans. Comput., Vol. C-28, No. 8, pp. 546-559, Aug. 1979.
  251. Parker, K.P., and E.J. McCluskey, "Sequential Circuit Output Probabilities from Regular Expressions," IEEE Trans. Comput., pp. 222-231, Mar. 1978. (CSL TR 93)
  252. McCluskey, E.J., K.P. Parker, and J.J. Shedletsky, "Boolean Network Probabilities and Network Design," IEEE Trans. Comput., Vol. C-27, No. 2, pp. 187-189, Feb. l978. (CSL TN 60)
  253. Dao, T.T., E.J. McCluskey, and L.K. Russell, "Multivalued Integrated Injection Logic," IEEE Trans. Comput., C-26, No. 12, pp. 1233-1241, Dec. 1977.
  254. McCluskey, E.J., "Editorial," Digital Processes, Vol. 3, No. 3, pp. 187-188, Autumn 1977.
  255. McCluskey, E.J., and R.C. Ogus, "Comparative Architecture of High Availability Computer Systems," COMPCON77, pp. 289-293, Feb. 28 - Mar. 3, 1977. (CSL TN 107)
  256. Dao, T.T., L.K. Russell, D.R. Preedy, and E.J. McCluskey, "Multilevel IIL with Threshold Gates," Proc., IEEE Int'l Solid-State Circuits Conf., pp. 110-112, Philadelphia, PA, Feb. 16-18, 1977.
  257. Wakerly, J.F., and E.J. McCluskey, "Microcomputers in the Computer Engineering Curriculum," Computer, Vol. 10, No. 1, pp. 32-38, Jan. 1977.
  258. McCluskey, E.J., "A Survey of Research at the Center for Reliable Computing, Stanford University," J. of Design Automation and Fault-Tolerant Computing, Vol. 1, No. 1, pp. 85-90, Oct. 1976. (CSL TN 96)
  259. Shedletsky, J.J., and E.J. McCluskey, "The Error Latency of a Fault in a Sequential Digital Circuit," FTCS-5, pp. 210-214; and IEEE Trans. Comput., C-25, No. 6, pp. 655-659, June 1976. (CSL TN 56)
  260. McCluskey, E.J., "Minimization of Boolean Functions," Bell System Tech. J., vol. 35, no. 5, pp. 1417-1444, Nov., 1956 and Computer Design Development, E.E. Swartzlander, Ed., Hayden Book Co., Inc., New Jersey, pp. 37-78, 1976.
  261. McCluskey, E.J., and R.C. Ogus, "Survey of Computer Reliability Studies," Electro-Technology, pp. 82-95, Dec. 1975.
  262. Shedletsky, J.J., and E.J. McCluskey, "The Error Latency of a Fault in a Combinational Digital Circuit," Digest, 1975 Int'l Symposium on Fault-Tolerant Computing, pp. 210-214, Paris, France, June 18-20, 1975.(CSL TN 55)
  263. McCluskey, E.J., "Micros, Minis, and Networks," Proc., Meeting on 20 Years of Computer Science, (CALCOLO, Supplemento N.1 - Vol. XII, Istitudo di Elaborazione della Informazione del CNR,) Pisa, Italy, pp. 23-33, June 16-19, 1975. (CSL TN 58)
  264. Parker, K.P., and E.J. McCluskey "Probabilistic Treatment of General Combinational Networks," IEEE Trans. Comput., Vol. C-24, No. 6, pp. 668-670, June 1975. (CSL TN 20)
  265. Parker, K.P., and E.J. McCluskey, "Analysis of Logic Circuits with Faults Using Input Signal Probabilities," IEEE Trans. Comput., Vol. C-24, No. 5, pp. 573-578, May 1975. (CSL TN 21)
  266. McCluskey, E.J., "Probability Models for Logic Networks," Proc., Fourth Manitoba Conference on Numerical Math, University of Manitoba, Winnipeg, Canada, pp. 21-28, Oct. 2-5, 1974.
  267. Usas, A.M., and E.J. McCluskey, "Design and Application of a Self-checking Periodic-signal Checker," COMPCON74, pp. 83-91, Sep. 10-12, 1974.
  268. Wakerly, J.F., and E.J. McCluskey, "Design of Low-cost General-purpose Self-diagnosing Computers," Information Processing Congress, Stockholm, Sweden, Aug. 5-10, 1974, Vol. 1, pp. 108-111. (CSL TN 38)
  269. Parker, K.P., and E.J. McCluskey, "Analysis of Logic Circuits with Faults Using Input Signal Probabilities," Digest, 1974 Int'l Symposium on Fault-Tolerant Computing, pp. 1.8-1.12, Urbana, IL, June 19-21, 1974.
  270. Reese, R.D., and E.J. McCluskey, "A Gate Equivalent Model for Combinational Logic Network Analysis," Dig., Third Ann. Symp. on Fault-Tolerant Computing, Palo Alto, CA, June 20-22, 1973, pp. 79-85. (CSL TN 28)
  271. Sloan, M., C.L. Coates, and E.J. McCluskey, "Cosine Survey of Electrical Engineering Departments," Computer, Vol. 6, No. 6, pp. 30-39, June 1973.
  272. Sloan, M., E.J. McCluskey, and C.L. Coates, "Cosine Survey of Electrical Engineering Departments," Cosine Committee, Commission on Education, May 1973.
  273. Siewiorek, D.P., and E.J. McCluskey, "Switch Complexity in Systems with Hybrid Redundancy," IEEE Trans. Comput., C-22, No. 3, Mar. 1973, pp. 276-282.
  274. Siewiorek, D.P., and E.J. McCluskey, "An Iterative Cell Switch Design for Hybrid Redundancy," IEEE Trans. Comput., C-22, No. 3, Mar. 1973, pp. 290-297.
  275. Siewiorek, D.P., and E.J. McCluskey, "An Iterative Cell Switch Design for Hybrid Redundancy," Digest, 1972 Int'l Symposium on Fault-Tolerant Computing, pp. 182-188, Newton, MA, June 19-21, 1972.
  276. Booth, T.L., C.G. Bell, C.H. Coker, R.M. Glorioso, E.J. McCluskey, F.J. Mowle, and D.M. Robinson, "Minicomputers in the Digital Laboratory Program," Consine Committee, Commission on Education, Apr. 1972.
  277. Siewiorek, D.P., and E.J. McCluskey, "Switch Designs for Hybrid Redundancy," Proc., Computer Systems Design - '72 West Conference, Anaheim, CA, Feb. 22-24, 1972.
  278. McCluskey, E.J., and F.W. Clegg, "Fault Equivalence in Combinational Logic Networks," IEEE Trans. Comput., C-20, No. 11, Nov. 1971, pp. 1286-1293. (CSL TN 10)
  279. Coates, C.L., B. Arden, T.C. Bartee, C.G. Bell, F.F. Kuo, E.J. McCluskey, and W.H. Surber, "An Undergraduate Computer Engineering Option for Electrical Engineering," Proc., IEEE, Vol. 59, No. 6, pp. 854-860, June 1971.
  280. Boute, R.T., and E.J. McCluskey, "Fault Equivalence in Sequential Machines," Symp. on Computers and Automata, Polytechnic of Brooklyn, Apr. 13-15, 1971, pp. 483-507. (CSL TR 15)
  281. Booth, T.L., S.M. Altman, F.W. Clegg, C.L. Coates, F.F. Coury, R.M. Glorioso, E.J. McCluskey, D.M. Robinson, and D.E. Troxel "Digital Systems Laboratory Courses and Laboratory Developments," Cosine Committee, Commission on Education, Mar. 1971.
  282. Clegg, F.W., and E.J. McCluskey, "The Algebraic Approach to Fault Logic Networks," Digest, 1971 Int'l Symposium on Fault-Tolerant Computing, pp. 44-45, Pasadena, CA, Mar. 1-3, 1971.
  283. McCluskey, E.J., "Test and Diagnosis Procedure for Digital Networks," Computer, Vol. 4, No. 1, pp. 17-20, Jan./Feb. 1971.
  284. Arden, B., T.C. Bartee, C.G. Bell, F.F. Kuo, E.J. McCluskey, W.H. Surber, and C.L. Coates, "An Undergraduate Computer Engineering Option for Electrical Engineering," Cosine Committee, Commission on Education, Jan. 1970.
  285. Bredt, T.H., and E.J. McCluskey, "Analysis and Synthesis of Control Mechanisms for Parallel Processes," in Parallel Processor Systems, Technologies, and Applications, pp. 287-295, L.C. Hobbs, Editor, Spartan Books, New York, New York, pp. 287-295, 1970.
  286. Bell, C.G., Y. Chu, C.L. Coates, W. Lichtenberger, F. Luconi, W. Viavant, and E.J. McCluskey, "An undergraduate Electrical Engineering Course on Computer Organization," Cosine Committee, Commission on Engineering Education, Oct. 1968.
  287. Atchison, W.F., S.D. Conte, J.W. Hamblen, T.E. Hull, T.A. Keenan, W.B. Kehl, E.J. McCluskey, S.O. Navarro, W.C. Rheinboldt, E.J. Schweppe, W. Viavant, and D.M. Young, "Curriculum 68," Communications of the ACM, Vol. II, No. 3, pp. 151-197, Mar. 1968.
  288. Dennis, J.B., D.C. Evans, W.H. Huggins, M. Karnaugh, J.F. Kaiser, F.F. Kuo, E.J. McCluskey, S. Seeley, W.H. Surber, M.E. Van Valkenberg and L.A. Zadeh, "Computer Sciences in Electrical Engineering," Cosine Committee, Commission of Engineering Education, Sep. 1967.
  289. Poage, J.F., and E.J. McCluskey, "Derivation of Optimum Test Sequences for Sequential Machines," Proc., 5th Annual Symposium on Switching Circuit Theory and Logical Design, S-164, pp. 121-128, IEEE Princeton, New Jersey, October 1964.
  290. Dolotta, T.A., and E.J. McCluskey, "The Coding of Internal States of Sequential Circuits," IEEE Trans. on Electronic Computers, Vol. EC-13, No. 5, pp. 549-562, October 1964.
  291. McCluskey, E.J., "Switching Functions," Progress in Circuit Theory - 1960-1963, L. Weinberg, Editor; IEEE Trans. on Circuit Theory, Vol. CT-11, No. 1, pp. 22-25, Mar. 1964.
  292. McCluskey, E.J., "Development of Switching Theory," Elektronische Rechenanlagen, Heft 6, Seite 249, 5 Jahrgang, Dec. 1963.
  293. McCluskey, E.J., "Logical Design Theory of NOR Gate Networks with No Complemented Inputs," Proc., 4th Annual Symposium on Switching Circuit Theory and Logical Design, S-156, pp. 137-148, IEEE, Chicago, IL, Sep. 1963.
  294. McCluskey, E.J., "Reduction of Feedback Loops in Sequential Circuits and Carry Leads in Iterative Networks," Information and Control, Vol. 6, No. 2, pp. 99-118, June 1963.
  295. Brzozowski, J.A., and E.J. McCluskey, "Signal Flow Graph Techniques for Sequential Circuit Diagrams," IEEE Trans. on Electronic Computers, Vol. EC-13, No. 2, pp. 67-76, Apr. 1963.
  296. McCluskey, E.J., "Minimum-State Sequential Circuits for a Restricted Class of Incompletely Specified Flow Tables," B.S.T.J., Vol. 41, No. 6, pp. 1759-1968, Nov. 1962.
  297. McCluskey, E.J., "Minimal Sums for Boolean Functions Having Many Unspecified Fundamental Products," Trans. AIEE, Pt. 1, Vol. 81 (Communications and Electronics), pp. 387-392, Nov. 1962.
  298. McCluskey, E.J., "Fundamental Mode and Pulse Mode Sequential Circuits," Proc., 2nd Int'l Federation on Information Processing Congress, pp. 725-730, Munich, West Germany, Aug. 27 - Sep. 1, 1962 (North-Holland Publishing Company, Amsterdam, Netherlands).
  299. Pyne, I.B., and E.J. McCluskey, "The Reduction of Redundancy in Solving Prime Implicant Tables," IRE Trans. on Electronic Computers, Vol. EC-11, No. 4, pp. 473-482, Aug. 1962.
  300. McCluskey, E.J., and H. Schorr, "Essential Multiple Output Prime Implicants," Proc., Symposium on Mathematical Theory of Automata, Vol. XII, pp. 437-457, Polytechnic Institute of Brooklyn, New York, New York, Apr. 1962.
  301. Pyne, I.B., and E.J. McCluskey, "An Essay on Prime Implicant Tables," Journal, Soc. Indus. and Applied Math,, Vol. 9, No. 4, pp. 604-631, Dec. 1961.
  302. Grasselli, A., and E.J. McCluskey, "Une Version Modifiee D'Algol Pour La Programmation Logique (1)," Proc., 2 eme Congress de 1'Association Francaise de Calcul et de Traitement de 1'Information, Paris, France, October 7-20, 1961.
  303. McCluskey, E.J., "Assignment of Carry Variables in Iterative Networks," Trans. AIEE, Pt. 1, Vol. 79 (Communications and Electronics), pp. 772-778, Jan. 1961.
  304. Paull, M.C., and E.J. McCluskey, "Boolean Functions Realizable with Single Threshold Devices," Proc., IRE, Vol. 48, No. 7, pp. 1335-1337, July 1960.
  305. Dolotta, T.A., and E.J. McCluskey, "Encoding of Incompletely Specified Boolean Matrices," Proc., Western Joint Computer Conference, Vol. 17, pp. 231-238, May 1960.
  306. McCluskey, E.J., "A Comparison of Sequential and Iterative Circuits," Trans. AIEE, Pt. 1, Vol. 78 (Communications and Electronics), pp. 1039-1044, Jan. 1960.
  307. McCluskey, E.J., and S.H. Unger, "A Note on the Number of Internal Variable Assignments for Sequential Switching Circuits," IRE Trans. On Electronic Computers, Vol. EC-8, No. 4, pp. 439-440, Dec. 1959.
  308. McCluskey, E.J., "Error-Correcting Codes - A Linear Programming Approach," B.S.T.J., Vol. 38, No. 6, pp. 1485-1512, Nov. 1959.
  309. McCluskey, E.J., "Iterative Combinational Switching Networks - General Design Considerations," IRE Trans. on Electronic Computers, Vol. EC-7, No. 4, pp. 285-291, Dec. 1958.
  310. Riekeman, E.C., A. Glovazky, and E.J. McCluskey, "Determination of Redundancies in a Set of Patterns," IRE Trans. on Information Theory, Vol. IT-3, No. 2, pp. 167-168, June 1957.
  311. McCluskey, E.J., "Detection of Group Invariance or Total Symmetry of a Boolean Function," B.S.T.J., Vol. 35, No. 6, pp. 1445-1453, Nov. 1956.
  312. McCluskey, E.J., "Minimization of Boolean Functions," B.S.T.J., Vol. 35, No. 6, pp. 1417-1444, Nov. 1956.

Refereed Journals and Conferences (accepted)

  1. "Algorithm-Based Fault Tolerance: A Performance Perspective Based on Error Rate," Int. Conf. on Dependable Systems and Networks (DSN'01) Fast Abstracts, Goteborg, Sweden, Jul. 1-4, 2001. (with A.A. Al-Yamani and N. Oh)
  2. "Low Energy Error Detection Technique Using Procedure Call Duplication," Int. Conf. on Dependable Systems and Networks (DSN'01) Fast Abstracts, Goteborg, Sweden, Jul. 1-4, 2001. (with N. Oh)
  3. "A Roll-Forward Recovery Scheme in TMR Systems for Real-Time Applications," Int. Conf. on Dependable Systems and Networks (DSN'01) Fast Abstracts, Goteborg, Sweden, Jul. 1-4, 2001. (with S.-Y. Yu)
  4. "Permanent Fault Repair in FPGAs through Graceful Degradation," Int. Conf. on Dependable Systems and Networks (DSN'01) Fast Abstracts, Goteborg, Sweden, Jul. 1-4, 2001. (with S.-Y. Yu)

[ Home | Professional Experience | Keynote and Plenary Addresses | PhDs Supervised | Technical Reports | Hat Photos ]


 


Last modified: Wed Aug 22 10:46:38 PDT 2001