PhDs Supervised

Edward J. McCluskey

Stanford University

  1. T.H. Bredt, Control of Parallel Processes, 1970
  2. F.W. Clegg, Algebraic Properties of Faults in Logic Networks, 1970
  3. D.D. Chamberlin, Parallel Implementation of a Single Assignment Language, 1971
  4. D.J. Chesarek, Fault Detecting Experiments for Sequential Machines, 1972
  5. S.H. Fuller, The Analysis and Scheduling of Devices Having Rotational Delays, 1972
  6. D.P. Siewiorek, Fault-Tolerant Computers Using Self-Diagnosis and Hybrid Redundancy, 1972
  7. R.T. Boute, Faults in Sequential Machines: Algebraic Properties and Detection Methods, 1973
  8. A.B. Salisbury, The Evaluation of Microprogram Implemented Emulators, 1973
  9. J.A. Abraham, Reliability Analysis of Digital Systems Protected by Massive Redundancy, 1974
  10. H. Mitarai, The Use of Semiconductor Read-Only Memory for Logic, 1974
  11. G.N. Shapiro, A Functional Approach to Structured Combinational-Logic Design, 1974
  12. L. Svobodova, Computer Performance Measurement and Evaluation Methods: Analysis and Applications, 1974
  13. J.F. Wakerly, Low-Cost Error Detection Techniques for Small Computers, 1974
  14. D.T. Wang, An Algorithm for the Generation of Test Sets for Combinational Logic Networks, 1974
  15. J. Losq, Modeling and Reliability of Redundant Digital Systems, 1975
  16. K.C.Y. Mei, Dominance Relations of Stuck-at and Bridging Faults in Logic Networks, 1975
  17. R.C. Ogus, Design and Evaluation of Ultra-Reliable Hybrid Redundant Digital Systems, 1975
  18. F.J. O.-Dias, Multiple Fault Analysis in Combinational Logic Circuits, 1975
  19. T.G. Price, Jr., Probability Models of Computer Systems, 1975
  20. S.G. Kolupaev, Cutting Planes and Self-Checking Networks, 1976
  21. K.P. Parker, Probabilistic Test Generation, 1976
  22. J.J. Shedletsky, Error Latency in Digital Circuits, 1976
  23. A.M. Usas, Error/Management in Digital Computer Input/Output Systems, 1976
  24. R. Betancourt, Analysis and Synthesis of Sequential Circuits Using Clocked Flip-Flops, 1977
  25. J. Savir, Detection of Intermittent Failures in Combinational Circuits, 1977
  26. M.D. Beaudry, Performance Considerations for the Reliability Analysis of Computing Systems, 1978
  27. M.L Blount, Probabilistic Fault Diagnosis Models for Digital Systems, 1978
  28. D. Lu, Concurrent Testing and Checking in Computer Systems, 1981
  29. S. Butner, Failures in Computers: A Study of Their Characteristics and a Tolerance Technique, 1981
  30. J. Khakbaz, Testing and Concurrent Checking for PLA's and Related Checker Design Issues, 1983
  31. M. Namjoo, Concurrent Testing at the Computer System Level, 1983
  32. S. Hassan, Design for Testability Techniques Using Signature Analysis, 1984
  33. S. Bozorgui-Nesbat, Design for Testability: Random Logic and Programmable Logic Arrays, 1985
  34. J.L.A. Hughes, Reliable Digital Systems: Multiple Fault Detection and Totally Self-Checking Comparators, 1986
  35. A. Mahmood, Concurrent Checking Using Watchdog Processors, 1986
  36. H. Amer, Computer Systems: Modeling and Reliability Issues, 1987.
  37. M.L. Côrtes, Temporary Failures in Digital Circuit: Experimental Results & Fault Modelling, 1987.
  38. D. Liu, Testable Structures for CMOS VLSI Circuits, 1987.
  39. L.-T. Wang, Circuits for Built-In Self-Test, 1987.
  40. K. Wagner, Digital Circuits: Random Testing and Testing Issues, 1987.
  41. J. Udell, Pseudo-Exhaustive Testing of Digital Integrated Circuits, 1988.
  42. S.D. Millman, Nonclassical Faults in CMOS Digital Integrated Circuits, 1989.
  43. N. Saxena, Test and Checker Data Compaction, 1991.
  44. H. Hao, Electrical Failure Modes in CMOS Logic Integrated Circuits, 1993.
  45. L. Avra, Synthesis Techniques for Built-in Self-Testable Designs, 1994.
  46. P. Franco, Testing Digital Circuits for Timing Failures by Output Waveform Analysis, 1994.
  47. S. Ma, Testing BiCMOS and Dynamic CMOS Logic, June 1995.
  48. S. Makar, Checking Experiments for Scan Chain Latches and Flip-Flops, June 1996.
  49. N. Touba, Synthesis Techniques for Pseudo-Random Built-In Self-Test, June 1996.
  50. R. Norwood, Sytnesis-for-Scan: Reducing Scan Overhead with High-Level Synthesis, Dec. 1997.
  51. T.Y.J. Chang, Voltage Screens for Early-Life Failures in CMOS Integrated Circuits, June 1998.
  52. S. Mitra, Diversity Techniques for Concurrent Error Detection, June 2000.
  53. N. Oh, Software Implemented Hardware Fault Tolerance, Dec. 2000.
  54. Huang, W.-J., Dependable Computing Techniques for Reconfigurable Hardware, June 2001.
  55. Shirvani, P.P., Fault-Tolerant Computing for Radiation Environments, June 2001.
  56. Yu, S.Y., Fault Tolerance in Adaptive Real-time Computing Systems, Dec. 2001.
  57. James Chien-Mo Li, Test and  Diagnosis of Open Defects in Digital CMOS Integrated Circuits, June 2002.
  58. Mehdi Baradaran Tahoori, Testing FPGAs, June 2003.
  59. Ahmad A. Al-Yamani, Deterministic Built-In Self-Test for Digital Circuits, April 2004.
  60. Erik Chmelar, The Test and Diagnosis of FPGAs, June 2004.
  61. Erik Volkerink, Design for Testability Techniques for Scan Compression, June 2004.

Princeton University

  1. M.H. Lewin, Negative-Resistance Elements as Digital Computer Components, 1960
  2. E.P. Stabler, Methods of Magnetic Logic, 1961
  3. T.A. Dolotta, The Coding Problem in the Design of Switching Circuits, 1961
  4. H. Schorr, Towards the Automatic Analysis and Synthesis of Digital Systems, 1962
  5. J.A. Brzozowski, Regular Expressions for Sequential Circuits, 1962
  6. J.F. Poage, The Derivation of Optimum Tests for Logic Circuits, 1962
  7. E.B. Eichelberger, Sequential Circuit Synthesis using Hazards and Delays, 1963
  8. J.F. Gimpel, Some Minimization Problems in the Design of Gate-Type Combinational Switching Networks
  9. A.D. Hall, Treatment of Delays in Asynchronous Networks


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    Last modified: Thu Jun 14 11:08:20 PDT 2001