Lectures

Edward J. McCluskey

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• Keynote and Plenary Addresses (Selected)

  • AT&T Conference on Electronic Testing (ACET 93), "Fads and Ethics in Test Research", Princeton, NJ, Sep. 27-28, 1993.
  • IEEE Int. Solid-State Circuits Conf., "Why We Need Design for Testability," San Francisco, CA, Feb. 13, 1991.
  • EURO ASIC 90, "Half a century of Logic Synthesis," Paris, France, May 29-31, 1990.
  • NCR Creating Reliable Products Conference, "Invited Keynote," Palo Alto, CA, Oct 11-14, 1988.
  • HP Design Technology Conference, DTC88, "IC Quality and Test Transparency", Monterey, CA, May 23-25, 1988.
  • Euromicro, "Comparing Causes of System Failure," Venice, Italy, Sept. 15, 1986.
  • II Congresso da SBmicro, "Test Requirements", , San Paulo, Brazil, July 1987.
  • "VLSI Design for Testability," 1984 Symposium on VLSI Technology , San Diego, CA, Sep. 10-12, 1984.
    Sixth Annual IEEE Workshop on Design for Testability, "Things Which Go Bump in the Night," Vail, CO, Apr. 1983.
  • IEEE Computer Elements Workshop, "Assurance of RAS for VLSI Systems," Dec. 1982.
  • International Symposium on Fault-Tolerant Computing (FTCS-12) "Test Questions," Santa Monica, CA, June 1982.
  • Fourth Annual International Conference on Fault-Tolerant Systems and Diagnostics, "Design for Testability Survey," Brno, Czechoslovakia, Sep. 28-30, 1981.
  • First Annual IEEE Workshop on Design for Testability, 1978.

• Distinguished Invited Lectures

  • "Digital IC Test Research Using Custom Chips," Special Seminar, Center for Reliable and High-Performance Computing, University of Illinois, June 1, 2001.
  • "CRC Research Activities," Credence Presentation, Fremont, CA, May 20, 1998.
  • "Can ATE Handle Next Generation Design?" Open Microphone Session, Panel Moderator, 1998 VLSI Test Symposium, Monterey, CA, Apr. 26-30, 1998.
  • "On-Line Testing, Industrial Practice and Perspectives," Panel Moderator, 1997 Int. Test Conf., Washington, DC, Nov. 1-6, 1997.
  • "Review of Current Research at Stanford University's Center for Reliable Computing," UC Berkeley CAD Seminar, Oct. 15, 1997.
  • "Scan Synthesis for One-Hot Signals," Fourth International Test Synthesis Workshop, Santa Barbara, CA, May 5-7, 1997. (with S. Mitra and L. Avra)
  • "Delay Testing of Data Paths with Scan," Fourth International Test Synthesis Workshop, Santa Barbara, CA, May 5-7, 1997. (with R.B. Norwood)
  • "Partial Isolation Rings for Testing Embedded Cores," 1996 IEEE Int. High Level Design Validation and Test Workshop, San Jose, CA, Nov. 14-15, 1996. (with N.A. Touba)
  • "Tops Synthesis Tool: A Design Framework for Dependable Computing Systems," Sun Microsystems, Menlo Park, CA, July 12, 1995.
  • "Tools for Dependable System Design and Evaluation," IFIP Working Group 10.4 Workshop, South Lake Tahoe, CA, June 23-26, 1995.
  • "Transformed Pseudo-Random Patterns for BIST," Built-In Self-Test/Design for Testability Workshop, Charleston, SC, Mar. 15-17, 1995. (with N.A. Touba)
  • "Fads and Ethics in Test Research," AT&T Conference on Electronic Testing (ACET 93), Princeton, NJ, Sep. 27-28, 1993.
  • "Very-high-level Synthesis and Built-in Self Test," CRHC Special Lecture Series, University of Illinois, Sep. 23, 1993.
  • "Why Computers Fail or Who Needs Design-for-Testability?," Distinguished Lecture Series, Texas A&M University, College Station, TX, April 23, 1993.
  • "Retrospective of the Computer Forum's Twenty-Five Years," Computer Forum 25th Annual Meeting, Stanford, CA, Feb. 23-25, 1993.
  • "Reducing the Performance Penalty of BIST," Office of Naval Research First Annual Workshop on Embedded Systems, Austin, TX, Jan. 11-13, 1993.
  • "Why Computers Fail or Who Needs Design for Testability?" Tandem, Austin, TX, Jan. 11, 1993.
  • "An Experiment to Evaluate Test Techniques," CRHC Special Lecture Series, University of Illinois, Sep. 17, 1992.
  • "Who Needs Design-for-Testability?" Systems Day on Campus, Stanford Computer Forum, Stanford, CA, June 11, 1992.
  • "Why Computers Fail and Who Needs Design-for-Testability?" Departments of Computer Science and Electrical and Computer Engineering, University of Arizona, Mar. 26, 1992.
  • "Clocking System Design," CRHC Special Lecture Series, University of Illinois, Oct. 31, 1991.
  • "Who Needs Design-for-Testability," Ottawa-Carleton Institute for Electrical Engineering Seminar, Ottawa, Canada, June 24, 1991.
  • "Who Needs Design-for-Testability," VLSI Seminar, T.J. Watson Research Center, Yorktown Heights, NY, June 16, 1991.
  • "Signature Analysis Design," Technology Seminar Series, IBM, Poughkeepsie, NY, May 15, 1991.
  • "Who Needs Design-for-Testability," Center for Reliable and High Performance Computing Seminar, University of Illinois, Apr. 22, 1991.
  • "Signature Analysis Design," Center for Reliable and High Performance Computing Seminar, University of Illinois, Apr. 19, 1991.
  • "Who Needs Design-for-Testability," CSE Distinguished Lecture Series on Computer-Aided Design, University of Michigan, Apr. 8, 1991.
  • "Design for Testability," ECE Graduate Colloquium, University of Iowa, Mar. 28, 1991.
  • "Signature Analysis Design," Coordinated Science Lab Seminar, University of Illinois, Oct. 30, 1990.
  • "Design for Test Overview," Microelectronic System Education Conference & Exposition, San Jose, CA , July 29 - Aug. 1, 1990.
  • "Reliable Advanced Electronic Systems," SDI/IST/ONR Reliable Advanced Electronic Systems Program, Stanford University, Stanford, CA, July 12-14, 1990.
  • "Pseudo-Exhaustive Testing and Why Synthesis Should Account for Multifaults," NSF-DARPA Synthesis Workshop, Boulder, CO, Jan. 26-29, 1990.
  • "Current Research on Reliable Systems," Coordinated Science Lab Seminar, University of Illinois, Oct. 30, 1989.
  • "Digital Test Principles," Tutorial, Int. Test Conf. 1989, Washington, DC, Aug. 28-31, 1989.
  • "A Self-Test and Self-Diagnosis Architecture for Boards Using Boundary Scans," IEEE Built-In Self-Test Workshop," Charleston, SC, Mar. 29-31, 1989. (with L.-T. Wang and M. Marhoefer)
  • "Design for Testability - Why and How," Sun Microsystems, Mt. View, CA, Mar. 23, 1989.
  • "Testability Measures, Ad Hoc, SFT, Scan, BIST," COMPCON Spring '89, Stanford University, Stanford, CA, Feb. 25, 1989.
  • "Testing Requirements, Fault Models, Required Fault Coverage," COMPCON Spring '89, Stanford University, Stanford, CA, Feb. 25, 1989.
  • "High Yield and Reliability at 10 8 Devices/Chip-What Does It Mean, and How Do We Archieve It?" IEDM, San Francisco, CA, Dec. 11-14, 1988.
  • "Production Testing of Digital Integrated Circuits," The Louisiana Distinguished Lecture Series, Lafayette, Louisiana, Nov. 4, 1988.
  • "Production Testing of Digital Integrated Circuits," CSDD Special Seminar, Honeywell, Nov. 2, 1988.
  • "Production Testing of Digital Integrated Circuits," Coordinated Science Lab Seminar, University of Illinois, Oct. 31, 1988.
  • "Invited Keynote," NCR Creating Reliable Products Conference, Palo Alto, CA, Oct. 11-14, 1988.
  • "Required Fault Coverage," The Institute of Control Problems, USSR Academy of Science, Moscow, USSR, Sep. 28, 1988.
  • "Required Fault Coverage," Institute of Electronics and Computer Science of Latvian Academy of Sciences, RIGA, Latria, Sep. 24, 1988.
  • "Undetected Bad Chips," USSR Academy of Science Institute of Information Transmission Problems, Moscow, USSR, Sep. 20, 1988.
  • "Digital Test Principles," Tutorial, Int. Test Conf. 1988, Washington, DC, Sep. 12-14, 1988.
  • "Pseudorandom Test Sequences," Rolm Mil-spec Computers, Aug. 10, 1988.
  • "Reliable Advanced Electronic Systems," SDIO/IST Contractor Review, July 28, 1988.
  • "Fault-Tolerant Computing Systems - Embedded Error Detectors and Correctors," Digital Equipment Corporation Seminar, July 25, 1988.
  • "IC Quality and Test Transparency," HP Design Technology Conference, DTC88, Monterey, CA, May 23-25, 1988
  • "IC Quality and Test Transparency," Oregon State University," May 9, 1988.
  • "IC Quality and Test Transparency," 1988 BIST Workshop," Kiawah Island, Charleston, SC, Mar. 23-25, 1988.
  • "Run-Time Failures - Causes and Cures," Digital Equipment Corporation Seminar, Mar. 22, 1988.
  • "Testing Perspectives," Sematech Test Workshop, Austin, TX, Mar. 14, 1988.
  • "IC Quality and Test Transparency," University of California Berkeley, Feb. 29, 1988.
  • "Probability Models for Pseudorandom Test Sequences," Tandem Computer, Cupertino, CA, Nov. 20, 1987.
  • "Electric System Reliability," Second SDIO Electronic Communication and Computer Panel Meeting, Monterey, CA, Nov. 17-18, 1987.
  • "Pseudorandom Test Sequences," Schlumberger Palo Alto Research, Sep. 15, 1987.
  • "Test Requirements," II Congresso da SBmicro, San Paulo, Brazil, July 1987.
  • "Pseudorandom Test Sequences," Tektronix Corp., Apr. 10, 1987.
  • "Research in Computer Science at Stanford," Presentation to Honeywell Corp., Mar. 16-17, 1987.
  • "Research in Fault-Tolerance and Testing and Reliability," Presentation to Honeywell Corp., Mar. 16-17, 1987.
  • "Why Bad Chips Go Undetected," Presentation to Hitachi Central Research Laboratories, Oct. 21, 1986.
  • "Why Bad Chips Go Undetected," Presentation to Fujitsu Laboratories, Inc., Oct. 20, 1986.
  • "VLSI Technology Research at Stanford," 20th IBM Computer Science Symposium, Japan, Oct. 10-12, 1986.
  • "Fault-Tolerant System and Computer Reliability," Presentation to NCR, Cairo, Egypt, Sep. 24, 1986.
  • "New Trends in Computers and the Importance of the Reliability Hardware and Software for Banking Business," Presentation to NCR Banking Division, Cairo, Egypt, Sep. 22, 1986.
  • "Testing Futures," 1986 Test Technology Curriculum Workshop, Washington, DC, Sep. 11, 1986.
  • "Basic Concepts and Techniques of Hardware Fault-Tolerance," Symposium on Computer Science, University of California Santa Cruz, Aug. 26, 1986.
  • "Comparing Causes of IC Failures," Univ. Mass Distinguished Lecture Series, May 15, 1986.
  • "How to Make Computers More Reliable," Department of Electrical and Computer Engineering Colloquium, University of New Mexico, Apr. 29, 1986.
  • "Why Bad ICs Get Through the Test Process," Sandia Corporation, Apr. 29, 1986.
  • "Fault Tolerant Computing Research at Stanford," Stanford University/TRW Colloquium, Apr. 11, 1986.
  • "Comparing Causes of IC Failures," Computer Forum: Tektronix Presentation, Beaverton, OR, Mar. 27, 1986.
  • "Fault Tolerant Computing Techniques," IEEE Santa Clara Valley Aerospace and Electronic Systems Chapter, Feb. 27, 1986.
  • "Pseudo-Exhaustive Testing," Tektronix COmputer Research Lab Colloquium Series, Feb. 1, 1986.
  • "Testing of VLSI Circuits," USC Computer Research Institute Distinguished Lecture Series, Sep. 19, 1985.
  • "VLSI-Oriented Built-in Self Test, " U. Illinois CSL Distinguished Lecturers Series, Sep. 4, 1985.
  • "VLSI Design for Testability," 1984 Symposium on VLSI Technology, San Diego, CA, Sep. 10-12, 1984.
  • "Testing IC-Systems," Electronic Design in the Late '80s, Electronic Industry Executive Seminar, Minneapolis, MN, Aug. 8-10, 1984.
  • "Pseudo-Exhaustive Testing for VLSI Devices," ATE Silicon Valley Conference, San Mateo, CA, Apr. 10-12, 1984.
  • Guest Speaker, Curriculum for Test Technology Workshop, Minneapolis, MN, Nov. 16-17, 1983.
  • "Design for Testability Survey," BIAS Microelettronica 1983, Milan, Italy, Feb. 23-25, 1983.
  • "Verification," SGS-ATES, Milan, Italy, May 28, 1982.
  • "Design for Testability," ENSIMAG, Grenoble, France, May 19, 1982.
  • "Design for Testability," LAAS, Toulouse, France, May 17, 1982.
  • "Testing," Trinity College, Dublin, Ireland, May 7, 1982.
  • "Fault-Tolerant Computing," University of Newcastle Upon Tyne, Newcastle Upon Tyne, England, May 4, 1982.
  • "Design for Testability," University of Edinburgh, Edinburgh, Scotland, May 3, 1982.
  • "Fault-Tolerant Computing," Computer Laboratory, Cambridge, England, Apr. 28, 1982.
  • "Design for Testability," Integrated Circuit Technologies for the 1980's, Continuing Education California Extension - Berkeley, San Francisco, CA, Feb. 5, 1982.
  • "design for Testability," Computer Forum Talk, NCR, San Diego, CA, Jan. 12, 1982.
  • "Verification Testing," Testing-of-Hardware Symposium, IBM T.J. Watson Research Center, Yorktown Heights, NY, Nov. 3-13, 1981.
  • "Multi-Valued Circuits," Computer Forum Talk, IBM Corporation, Kingston, NY, Nov. 3, 1981.
  • "Design for Testability," Queen Mary College, University of London, London, England, Oct. 30, 1981.
  • "Design for Testability," Agence de l'Informatique, Paris, France, Oct. 23, 1981.
  • "Multiple-Valued Logic Circuits," Computer Forum Talk, Siemens Corporation, Munich, Germany, Oct. 15, 1981.
  • "Fault-Tolerant Computer Systems," Technical University of Budapest, Budapest, Hungary, Oct. 12, 1981.
  • "Microprocessor Testing," Institute for Coordination of Computer Techniques, Budapest, Hungary, Oct. 8, 1981.
  • "Test Pattern Generation," Tenth CANDE Workshop, Gravenhurst, Ontario, Canada, Sep. 20-22, 1981.
  • "Testing VHSIC Devices," First Annual VHSIC Program Review, Arlington, VA, June 15-19, 1981.
  • "Multivalued Logic and Design for Testability," Computer Form Lecture, Siemens Corporation, Cherry Hill, NJ, June 17, 1981.
  • "Reliable Computing Systems," Lockheed Stanford Microelectronics Symposium, Lockheed Palo Alto Research Laboratory, Palo Alto, CA, May 26-27, 1981.
  • "Testing Digital ICs," Integrated Circuit Technologies for the 1980s, Lifelong Learning, Continuing Education in Engineering, University Extension, and the College of Engineering, University of California, Berkeley; Palo Alto, CA, Feb. 3-4, 1981.
  • "Fault-Tolerant Computing," Fast Turn-Around Fabrication Group Meeting, Stanford University, Stanford, CA, Nov. 26, 1980.
  • "Design for Autonomous Test," Computer Forum Lecture, IBM - T.J. Watson Research Center, Yorktown Heights, NY, Nov. 6, 1980.
  • "Testing Digital Circuits and Systems," presented at various institutions during a visit to Beijing, Xian, and Shanghai, People's Republic of China, Sep. 19-30, 1980.
  • "Fault Tolerant Computing," Honeywell Worldwide Directors of Engineering and Technology Conference, Scottsdale, AZ, Feb. 5, 1980.
  • "Testing and Diagnosis of Logic," Invited Paper, Euro/IFIP 79, P.A. Samet, Editor, London, England, Sep. 25-28, 1979.
  • "Logic Design of Quad IIL Circuits," IBM - T.J. Watson Research Center, Yorktown Heights, New York, July 11, 1979.
  • "Fault-Tolerant Computer Systems," CS Colloquium, Computer Science Dept., Stanford University, Stanford, CA, May 29, 1979.
  • "Fault-Tolerant Digital Systems," IEEE Computer Society, Beaverton, OR, Apr. 20, 1979.
  • "Fault-Tolerant Design Techniques," Dept. of Computer Science, Duke University, Durham, NC, Feb. 2, 1979.
  • "Multi-Valued Logic Systems Using IIL Techniques," North Carolina State University, Raleigh, NC, Feb. 1, 1979.
  • "Logic Design for Multi-Level Integrated Circuits," Distinguished Lecturer Series, Computer Science Dept., Carnegie-Mellon University, Pittsburgh, PA, Mar. 8, 1978.
  • "Multi-Value Threshold Logic," Dept. of Electrical Engineering, Stanford University, Stanford, CA, Jan. 19, 1978.
  • "Probability Models for Logic Networks," Fourth Manitoba Conf. on Numerical Mathematics, pp. 21-28, Winnipeg, Canada, Oct. 2-5, 1974.
  • "Micros, Minis and Networks," 20th Anniv. of Computer Science, Pisa, Italy, June 1974.
  • IBM Scientific Computing Symposium: Computer-Aided Experimentation, Session Chairman, TJ Watson Research Center, Yorktown Heights, New York, Oct. 12, 1965.
  • VI Annual Symposium on Switching Circuit Theory and Logical Design, Session Chairman, University of Michigan, Oct. 7, 1965.
  • "Computer Science and Electrical Engineering," Sagamore Conference (IEEE Group on Education and Syracuse University) on Electrical Engineering in a Symbolic World, June 11, 1965.
  • Commentator, "Special Session on Mathematical Theory of Automatic and Switching Theory," IFIP Congress '65, May 28, 1965.
  • "Computers in Modern Society," Montclair Adult School, Mar. 16, 1965.
  • "Computer Sciences and Electrical Engineering at Princeton," Meeting on Computer Sciences in Electrical Engineering, Berkeley, CA, Feb. 12, 1965.
  • "A Review of Switching Theory," Dept. of Electrical Engineering Colloquium, New York University, Jan. 5, 1965.
  • "Modes of Sequential Circuit Operation," Digital Computer Laboratory Colloquim, University of Illinois, Nov. 23, 1964.
  • "A Review of Switching Theory," Dept. of Electrical Engineering Seminar, University of Notre Dame, Oct. 2, 1964.
  • "Course on the Theory of the Computer," Princeton Adult School, Sept. 24-Nov. 26, 1964.
  • "Minimization Theory for Combinational and Sequential Circuits," Short Course on Switching Theory, Computer Logic and Automatic Studies, University of Southern California, July 9-10, 1964.
  • "Fundamental Mode and Pulse Mode Sequential Circuits," Proc., 2nd Int'l Federation on Information Processing Congress, pp. 725-730, Munich, West Germany, 1962.

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